Patents by Inventor Keiichi Handa

Keiichi Handa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220261756
    Abstract: According to one embodiment, an information processing apparatus includes processing circuitry. The processing circuitry is configured to combine a sell condition under which a first dealer sells a product and a buy condition under which a second dealer buys the product on a basis of information of a first transport medium to transport the product, and generate matching information including the sell condition and the buy condition combined each other; and assign a transport of the product to the first transport medium by associating the transport with the first transport medium and perform scheduling of the transport on a basis of the matching information.
    Type: Application
    Filed: September 9, 2021
    Publication date: August 18, 2022
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Shigeta KUNINOBU, Keiichi HANDA, Takufumi YOSHIDA
  • Publication number: 20080104567
    Abstract: There is provided an apparatus that creates a component allocation plan for an electronic apparatus including first and second allocation layers in which components are allocated, including: a storage configured to store first and second component information indicating sizes of a plurality of first components and a plurality of second components to be allocated in the first and second allocation layer; an allocation order determiner configured to determine first and second allocation orders in which the first and second components are allocated for each layer; an allocation strategy determiner configured to determine first and second allocation strategies by which the first and second components are allocated, which are different each other; and a component allocating unit configured to allocate the first and second components in the first and second allocation layer in accordance with the first and second allocation orders and the first and second allocation strategies.
    Type: Application
    Filed: October 26, 2007
    Publication date: May 1, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Shigeta Kuninobu, Keiichi Handa
  • Publication number: 20050065867
    Abstract: A demand-and-supply intervening system which supports determination of a demand-and-supply relationship between users in association with demand resources and supply resources between a plurality of users, comprises an entry acquisition unit for creating an entry set by collecting a plurality of entries each of which has a plurality of resources as demand/supply objects and a combinatorial condition to be satisfied between resources, and a candidate group determination unit for extracting a candidate group of entries so that all entries included in the candidate group satisfy combinatorial conditions included in each entry when extracting the candidate group having a plurality of entry which includes at least one entry designated as a base point, and determining the presence/absence of demand-and-supply relationships between demand and supply resources between entries which belong to the candidate group and demand-and-supply quantities.
    Type: Application
    Filed: July 23, 2004
    Publication date: March 24, 2005
    Inventors: Hideyuki Aisu, Keiichi Handa, Toshiaki Tanaka, Tomoshi Otsuki
  • Patent number: 6598222
    Abstract: An apparatus for supporting parallelization according to the invention is characterized by comprising a serialization unit for converting a first concurrent program having a concurrent structure into a sequential program capable of being sequentially executed, a debugging unit for debugging the sequential program and forming debugging information, and a concurrent program programming unit for performing parallelization of the debugged sequential program on the basis of the debugging information to convert the sequential program into a second concurrent program. With above configuration, the debugging unit includes a unit for introducing information associated with concurrency to the sequential program.
    Type: Grant
    Filed: April 27, 2001
    Date of Patent: July 22, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Naoshi Uchihira, Shinichi Honiden, Akihiko Ohsuga, Toshibumi Seki, Yasuo Nagai, Keiichi Handa, Satoshi Ito, Nobuyuki Sawashima, Yasuyuki Tahara, Hideaki Shiotani
  • Publication number: 20010020293
    Abstract: An apparatus for supporting parallelization according to the invention is characterized by comprising serialization unit for converting a first concurrent program having a concurrent structure into a sequential program capable of being sequentially executed, debugging unit for debugging the sequential program and forming debugging information, and concurrent program programming unit for performing parallelization of the debugged sequential program on the basis of the debugging information to convert the sequential program into a second concurrent program. With above configuration, the debugging unit includes unit for introducing information associated with concurrency to the sequential program.
    Type: Application
    Filed: April 27, 2001
    Publication date: September 6, 2001
    Inventors: Naoshi Uchihira, Shinichi Honiden, Akihiko Ohsuga, Toshibumi Seki, Yasuo Nagai, Keiichi Handa, Satoshi Ito, Nabuyuki Sawashima, Yasuyuki Tahara, Hideaki Shiotani
  • Patent number: 6275980
    Abstract: An apparatus for supporting parallelization according to the invention is characterized by comprising a serialization unit for converting a first concurrent program having a concurrent structure into a sequential program capable of being sequentially executed, a debugging unit for debugging the sequential program and forming debugging information, and a concurrent program programming unit for performing parallelization of the debugged sequential program on the basis of the debugging information to convert the sequential program into a second concurrent program. With above configuration, the debugging unit includes a unit for introducing information associated with concurrency to the sequential program.
    Type: Grant
    Filed: July 8, 1998
    Date of Patent: August 14, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Naoshi Uchihira, Shinichi Honiden, Akihiko Ohsuga, Toshibumi Seki, Yasuo Nagai, Keiichi Handa, Satoshi Ito, Nobuyuki Sawashima, Yasuyuki Tahara, Hideaki Shiotani
  • Patent number: 6067259
    Abstract: A fault repair method including the steps of providing second memory cells as spare lines for repairing faulty elements of first memory cells for storing data therein, setting virtual third memory cells with respect to a repair target including said first memory cells and the second memory cells, and repairing the faulty elements of the first memory cells and the second memory cells by using the virtual third cells.
    Type: Grant
    Filed: June 9, 1998
    Date of Patent: May 23, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Keiichi Handa, Kazuhito Haruki
  • Patent number: 5860009
    Abstract: An apparatus for supporting parallelization according to the invention is characterized by comprising a serialization unit for converting a first concurrent program having a concurrent structure into a sequential program capable of being sequentially executed, a debugging unit for debugging the sequential program and forming debugging information, and a concurrent program programming unit for performing parallelization of the debugged sequential program on the basis of the debugging information to convert the sequential program into a second concurrent program. With above configuration, the debugging unit includes a unit for introducing information associated with concurrency to the sequential program.
    Type: Grant
    Filed: April 27, 1995
    Date of Patent: January 12, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Naoshi Uchihira, Shinichi Honiden, Akihiko Ohsuga, Toshibumi Seki, Yasuo Nagai, Keiichi Handa, Satoshi Ito, Nobuyuki Sawashima, Yasuyuki Tahara, Hideaki Shiotani
  • Patent number: 5465218
    Abstract: An LSI element placement method of placing elements in accordance with an order in which branches are arranged, each branch being constituted by an element array included in a circuit diagram having first and second terminals, the method including a partial circuit extraction step of sequentially extracting data of a predetermined number of branches included in the circuit diagram from the first terminal side of the circuit diagram so as to overlap the data by a predetermined number, and an element placement step of performing an element placement operation based on a genetic algorithm in the extracted partial circuit data, thereby generating an element placement result including placement coordinate data of all elements included in the partial circuit data.
    Type: Grant
    Filed: February 10, 1994
    Date of Patent: November 7, 1995
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Keiichi Handa