Abstract: An electrode structure includes: a plurality of pixel electrodes arranged separately from each other; and a plurality of dielectric layers laminated in a first direction with respect to the plurality of pixel electrodes, in which the plurality of dielectric layers includes: a first dielectric layer that spreads over the plurality of pixel electrodes in a direction intersecting with the first direction; and a second dielectric layer that includes dielectric material having a refractive index higher than that of the first dielectric layer, sandwiches the first dielectric layer together with the plurality of pixel electrodes, and has a slit at a position overlapping space between pixel electrodes adjacent when viewed from the first direction.

Abstract: To provide a technique capable of improving reliability of a semiconductor device having a nonvolatile memory cell by suppressing the reduction of the drive force. A memory cell is configured by a selection pMIS having a selection gate electrode including a conductive film exhibiting a p-type conductivity and a memory pMIS having a memory gate electrode including a conductive film exhibiting a p-type conductivity, and at the time of write, hot electrons are injected into a charge storage layer from the side of a semiconductor substrate 1 and at the time of erase, hot holes are injected into the charge storage layer from the memory gate electrode.

Abstract: The present invention aims to enhance the reliability of a semiconductor device having first through fourth capacitive elements. The first through fourth capacitive elements are disposed over a semiconductor substrate. A series circuit of the first and second capacitive elements and a series circuit of the third and fourth capacitive elements are coupled in parallel between first and second potentials. Lower electrodes of the first and third capacitive elements are respectively formed by a common conductor pattern and coupled to the first potential. Lower electrodes of the second and fourth capacitive elements are respectively formed by a conductor pattern of the same layer as the above conductor pattern and coupled to the second potential. Upper electrodes of the first and second capacitive elements are respectively formed by a common conductor pattern and brought to a floating potential.

Abstract: To provide a technique capable of improving reliability of a semiconductor device having a nonvolatile memory cell by suppressing the reduction of the drive force. A memory cell is configured by a selection pMIS having a selection gate electrode including a conductive film exhibiting a p-type conductivity and a memory pMIS having a memory gate electrode including a conductive film exhibiting a p-type conductivity, and at the time of write, hot electrons are injected into a charge storage layer from the side of a semiconductor substrate 1 and at the time of erase, hot holes are injected into the charge storage layer from the memory gate electrode.

Abstract: The present invention aims to enhance the reliability of a semiconductor device having first through fourth capacitive elements. The first through fourth capacitive elements are disposed over a semiconductor substrate. A series circuit of the first and second capacitive elements and a series circuit of the third and fourth capacitive elements are coupled in parallel between first and second potentials. Lower electrodes of the first and third capacitive elements are respectively formed by a common conductor pattern and coupled to the first potential. Lower electrodes of the second and fourth capacitive elements are respectively formed by a conductor pattern of the same layer as the above conductor pattern and coupled to the second potential. Upper electrodes of the first and second capacitive elements are respectively formed by a common conductor pattern and brought to a floating potential.

Abstract: A reduction in size nonvolatile semiconductors for use in a memory device and an increase in the capacity thereof are promoted. Each memory cell of a flash memory is provided with a field effect transistor having a first gate insulator film formed on a p-type well, a selector gate which is formed on the first insulator film and has side faces and a top face covered with a silicon oxide film (first insular film), floating gates which are formed in a side-wall form on both sides of the selector gate and which are electrically isolated from the selector gate through the silicon oxide film, a second gate insulator film formed to cover the silicon oxide film and the surface of each of the floating gates, and a control gate formed over the second gate insulator film.

Abstract: An AND flash memory of the type wherein a memory cell is constituted of n-type semiconductor regions (a source and a drain) formed in a p-type well of a semiconductor substrate and three gates (including a floating gate, a control gate and a selective gate) is manufactured. In the manufacture, arsenic (As) is introduced into a p-type well in the vicinity of one of side walls of the selective gate to form n-type semiconductor regions (a source and a drain). Thereafter, to cope with a drain disturb problem, the substrate is thermally treated by use of an ISSG (In-Situ Steam Generation) oxidation method so that a first gate, insulating film disposed in the vicinity of one of side walls, at which the n-type semiconductor regions have been formed, is formed thick.

Abstract: A non-volatile semiconductor memory device provides for higher integration by reducing the area of occupation of direct peripheral circuits, in which the memory cell of an AND type flash memory includes a selection gate, a float gate, a control gate that functions as a word line, and an n-type semiconductor region (source, drain) that functions as a local bit line. A pair of local bit lines adjacent to each other in a memory mat are connected with one global bit line at one end in the direction of the column of the memory mat, and a selection MOS transistor, formed by one enhancement type MOS transistor and one depletion type MOS transistor; is connected in series with each of the pair of local bit lines. One of the local bit lines is selected by turning the selection MOS transistor on/off.

Abstract: A reduction in size nonvolatile semiconductors for use in a memory device and an increase in the capacity thereof are promoted. Each memory cell of a flash memory is provided with a field effect transistor having a first gate insulator film formed on a p-type well, a selector gate which is formed on the first insulator film and has side faces and a top face covered with a silicon oxide film (first insular film), floating gates which are formed in a side-wall form on both sides of the selector gate and which are electrically isolated from the selector gate through the silicon oxide film, a second gate insulator film formed to cover the silicon oxide film and the surface of each of the floating gates, and a control gate formed over the second gate insulator film.

Abstract: A reduction in size nonvolatile semiconductors for use in a memory device and an increase in the capacity thereof are promoted. Each memory cell of a flash memory is provided with a field effect transistor having a first gate insulator film formed on a p-type well, a selector gate which is formed on the first insulator film and has side faces and a top face covered with a silicon oxide film (first insular film), floating gates which are formed in a side-wall form on both sides of the selector gate and which are electrically isolated from the selector gate through the silicon oxide film, a second gate insulator film formed to cover the silicon oxide film and the surface of each of the floating gates, and a control gate formed over the second gate insulator film.

Abstract: A process for producing a water-developable printing plate for use in relief printing, comprising subjecting a solid plate made of a photosensitive resin composition including at least (a) a hydrophilic resin, (b) a hydrophobic resin, (c) a photopolymerizable unsaturated compound and (d) a photopolymerization initiator to at least an exposure step with actinic light, a development step and a post-exposure step, wherein the above described post-exposure step is carried out in a low oxygen concentration environment.

Abstract: At least not less than one capacitor formation trench providing an uneven surface is formed on the surface of a capacitor formation region. Thus, the surface area of a capacitor is increased, which enables improvement of the capacitance of the capacitor per unit area. Further, by forming the capacitor formation trench and an element formation trench that are formed in the surface of the semiconductor substrate by the same step, it is possible to simplify the manufacturing process. Whereas, a dielectric film of the capacitor in the capacitor formation region and a high-voltage gate insulating film in a MISFET formation region are formed by the same step; alternatively, the dielectric film of the capacitor in the capacitor formation region and a memory gate interlayer film between a polysilicon layer and a polysilicon layer in the memory cell formation region are formed by the same step.

Abstract: At least not less than one capacitor formation trench providing an uneven surface is formed on the surface of a capacitor formation region. Thus, the surface area of a capacitor is increased, which enables improvement of the capacitance of the capacitor is increased, which enables improvement of the capacitance of the capacitor per unit area. Further, by forming the capacitor formation trench and an element formation trench that are formed in the surface of the semiconductor substrate by the same step, it is possible to simplify the manufacturing process. Whereas, a dielectric film of the capacitor in the capacitor formation region and a high-voltage insulating film in a MISFET formation region are formed by the same step; alternatively, the dielectric of the capacitor in the capacitor formation region and a memory gate interlayer film between a polysilicon layer and a polysilicon layer in the memory cell formation region are formed by the same step.

Abstract: A reduction in size nonvolatile semiconductors for use in a memory device and an increase in the capacity thereof are promoted. Each memory cell of a flash memory is provided with a field effect transistor having a first gate insulator film formed on a p-type well, a selector gate which is formed on the first insulator film and has side faces and a top face covered with a silicon oxide film (first insular film), floating gates which are formed in a side-wall form on both sides of the selector gate and which are electrically isolated from the selector gate through the silicon oxide film, a second gate insulator film formed to cover the silicon oxide film and the surface of each of the floating gates, and a control gate formed over the second gate insulator film.

Abstract: A non-volatile semiconductor memory device provides for higher integration by reducing the area of occupation of direct peripheral circuits, in which the memory cell of an AND type flash memory includes a selection gate, a float gate, a control gate that functions as a word line, and an n-type semiconductor region (source, drain) that functions as a local bit line. A pair of local bit lines adjacent to each other in a memory mat are connected with one global bit line at one end in the direction of the column of the memory mat, and a selection MOS transistor, formed by one enhancement type MOS transistor and one depletion type MOS transistors is connected in series with each of the pair of local bit lines. One of the local bit lines is selected by turning the selection MOS transistor on/off.

Abstract: An AND flash memory of the type wherein a memory cell is constituted of n-type semiconductor regions (a source and a drain) formed in a p-type well of a semiconductor substrate and three gates (including a floating gate, a control gate and a selective gate) is manufactured. In the manufacture, arsenic (As) is introduced into a p-type well in the vicinity of one of side walls of the selective gate to form n-type semiconductor regions (a source and a drain). Thereafter, to cope with a drain disturb problem, the substrate is thermally treated by use of an ISSG (In-Situ Steam Generation) oxidation method so that a first gate,insulating film disposed in the vicinity of one of side walls, at which the n-type semiconductor regions have been formed, is formed thick.

Abstract: The present invention provides a technology which allows the improvement of the capacitor capacitance per unit area, and a technology which allows the simplification of a manufacturing process associated therewith. At least not less than one capacitor formation trench causing the uneven surface is formed on the surface of a capacitor formation region. As a result, the surface area of a capacitor is increased, which enables the improvement of the capacitance of the capacitor per unit area. Further, by forming the capacitor formation trench and an element formation trench formed in the surface of the semiconductor substrate are formed by the same step. As a result, it is possible to simplify the manufacturing process. Whereas, a dielectric film of the capacitor in the capacitor formation region and a high-voltage gate insulating film in a MISFET formation region are formed by the same step.

Abstract: A water-developable, photosensitive resin plate for letterpress printing which comprises a photosensitive resin layer and a protective film contacting therewith, wherein the protective film consists of at least two layers, of which one is a surface layer containing a resin having a water absorption of 5% by weight or less and the other is an intermediate layer containing a water-soluble resin in contact with the photosensitive resin layer.

Abstract: A water-developable, photosensitive resin plate for letterpress printing which comprises a photosensitive resin layer and a protective film contacting therewith, wherein the protective film consists of at least two layers, of which one is a surface layer containing a resin having a water absorption of 5% by weight or less and the other is an intermediate layer containing a water-soluble resin in contact with the photosensitive resin layer.

Abstract: A semiconductor light-emitting device includes a plurality of semiconductor rods, each of which has a pn junction. The semiconductor rods are formed on a semiconductor substrate such that the plurality of semiconductor rods are arranged at a distance substantially equal to an integer multiple of the wavelength of light emitted from the semiconductor rod. With such devices, various novel optical devices such as a micro-cavity laser of which the threshold current is extremely small and a coherent light-emitting device having no threshold value can be realized.