Patents by Inventor Keiichi Higashitani
Keiichi Higashitani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20050112832Abstract: A thermal process for activating respective impurities in a polysilicon film to be a gate electrode and a resistance element is performed with the polysilicon film to be the gate electrode and the resistance element being coated with an oxide film, after the respective impurities are implanted into the polysilicon film to be the gate electrode and the resistance element. Here, concentrations of the respective impurities in the polysilicon film to be the gate electrode and the resistance element are adjusted by controlling the thickness of the oxide film. The degree of impurity activation is thereby adjusted.Type: ApplicationFiled: November 8, 2004Publication date: May 26, 2005Applicant: RENESAS TECHNOLOGY CORP.Inventors: Hiroshi Kawashima, Motoshige Igarashi, Keiichi Higashitani
-
Publication number: 20050062099Abstract: A semiconductor device and a manufacturing method thereof permitting the quality of gate insulating films to be prevented from deteriorating and thereby permitting electrical characteristics of the device to be prevented from deteriorating are provided. In a semiconductor device including a plurality of field effect transistors, an oxidation protection film 21 is formed on a side of one gate electrode 19.Type: ApplicationFiled: November 5, 2004Publication date: March 24, 2005Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Kenji Yoshiyama, Motoshige Igarashi, Keiichi Yamada, Katsuya Okada, Keiichi Higashitani
-
Patent number: 6853030Abstract: A semiconductor device and a manufacturing method thereof permitting the quality of gate insulating films to be prevented from deteriorating and thereby permitting electrical characteristics of the device to be prevented from deteriorating are provided. In a semiconductor device including a plurality of field effect transistors, an oxidation protection film 21 is formed on a side of one gate electrode 19.Type: GrantFiled: February 24, 2003Date of Patent: February 8, 2005Assignee: Renesas Technology Corp.Inventors: Kenji Yoshiyama, Motoshige Igarashi, Keiichi Yamada, Katsuya Okada, Keiichi Higashitani
-
Patent number: 6841459Abstract: A thermal process for activating respective impurities in a polysilicon film to be a gate electrode and a resistance element is performed with the polysilicon film to be the gate electrode and the resistance element being coated with an oxide film, after the respective impurities are implanted into the polysilicon film to be the gate electrode and the resistance element. Here, concentrations of the respective impurities in the polysilicon film to be the gate electrode and the resistance element are adjusted by controlling the thickness of the oxide film. The degree of impurity activation is thereby adjusted.Type: GrantFiled: November 6, 2002Date of Patent: January 11, 2005Assignee: Renesas Technology Corp.Inventors: Hiroshi Kawashima, Motoshige Igarashi, Keiichi Higashitani
-
Publication number: 20030216015Abstract: A thermal process for activating respective impurities in a polysilicon film to be a gate electrode and a resistance element is performed with the polysilicon film to be the gate electrode and the resistance element being coated with an oxide film, after the respective impurities are implanted into the polysilicon film to be the gate electrode and the resistance element. Here, concentrations of the respective impurities in the polysilicon film to be the gate electrode and the resistance element are adjusted by controlling the thickness of the oxide film. The degree of impurity activation is thereby adjusted.Type: ApplicationFiled: November 6, 2002Publication date: November 20, 2003Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Hiroshi Kawashima, Motoshige Igarashi, Keiichi Higashitani
-
Patent number: 6620666Abstract: There is described a method of manufacturing a semiconductor device of dual-gate construction, which method prevents occurrence of a highly-resistant local area in a gate electrode of dual-gate construction. A polysilicon layer which is to become a conductive layer of a gate electrode of dual-gate construction is formed on an isolation oxide film. N-type impurities are implanted into an n-type implantation region of the polysilicon film while a photoresist film is taken as a mask. P-type impurities are implanted into a p-type impurity region of the polysilicon film 3 while another photoresist film is taken as a mask. Implantation of n-type impurities and implantation of p-type impurities are performed such that an overlapping area to be doped with these impurities in an overlapping manner is inevitably formed.Type: GrantFiled: January 23, 2001Date of Patent: September 16, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Kenji Yoshiyama, Keiichi Higashitani, Masao Sugiyama
-
Publication number: 20030151099Abstract: A semiconductor device and a manufacturing method thereof permitting the quality of gate insulating films to be prevented from deteriorating and thereby permitting electrical characteristics of the device to be prevented from deteriorating are provided. In a semiconductor device including a plurality of field effect transistors, an oxidation protection film 21 is formed on a side of one gate electrode 19.Type: ApplicationFiled: February 24, 2003Publication date: August 14, 2003Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Kenji Yoshiyama, Motoshige Igarashi, Keiichi Yamada, Katsuya Okada, Keiichi Higashitani
-
Patent number: 6541823Abstract: A semiconductor device and a manufacturing method thereof permitting the quality of gate insulating films to be prevented from deteriorating and thereby permitting electrical characteristics of the device to be prevented from deteriorating are provided. In a semiconductor device including a plurality of field effect transistors, an oxidation protection film 21 is formed on a side of one gate electrode 19.Type: GrantFiled: March 11, 1998Date of Patent: April 1, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Kenji Yoshiyama, Motoshige Igarashi, Keiichi Yamada, Katsuya Okada, Keiichi Higashitani
-
Patent number: 6531737Abstract: A silicon semiconductor substrate has a plurality of active regions having an impurity region and an isolating region which electrically isolates these active regions from each other. The isolating region is formed of a silicon nitride film. A contact hole penetrates an interlayer insulating film and reaches an impurity region. In this semiconductor device, when the contact hole falls across the impurity region and the isolating region, an amount of erosion in the isolating region is reduced.Type: GrantFiled: December 10, 1998Date of Patent: March 11, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Masakazu Okada, Keiichi Higashitani, Hiroshi Kawashima
-
Publication number: 20030015798Abstract: A method of fabricating a semiconductor device includes burying Cu wiring with an insulating interlayer film and a first insulating film for preventing diffusion of copper on a planarized surface, including the Cu wiring, of which copper is the uppermost layer, and with a second insulating film having high moisture resistance. A photosensitive polyimide material is applied to the insulating film, exposed, and developed, thereby forming an etching mask. The etching mask is cured. Using the cured etching mask, the insulating films are etched to expose the Cu wiring as the uppermost layer.Type: ApplicationFiled: July 15, 2002Publication date: January 23, 2003Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Hideyo Haruhana, Keiichi Higashitani, Hiroyuki Amishiro, Masazumi Matsuura
-
Publication number: 20020180047Abstract: A method of fabricating a semiconductor device includes following four steps. (1) Cu wiring is buried in an insulating interlayer film, an insulating film for preventing diffusion of copper is deposited on a planarized surface including the Cu wiring as the uppermost layer, and another insulating film having high moisture resistance is deposited. (2) On the insulating film, a photosensitive polyimide material is applied, exposed, and developed, thereby forming an etching mask. (3) The etching mask is cured. (4) By using the cured etching mask, the insulating films are etched to expose the Cu wiring as the uppermost layer.Type: ApplicationFiled: July 15, 2002Publication date: December 5, 2002Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Hideyo Haruhana, Keiichi Higashitani, Hiroyuki Amishiro
-
Patent number: 6479873Abstract: A semiconductor device more reduced in size and a manufacturing method thereof are provided. A gate electrode is covered with a silicon nitride film having a selecting ratio greater than an NSG film under a prescribed etching condition. A cobalt suicide film is formed on an upper surface of source/drain regions. Furthermore, a refractory metal silicide film forming the gate electrode is formed by a cobalt silicide film.Type: GrantFiled: November 22, 1999Date of Patent: November 12, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Kenji Yoshiyama, Keiichi Higashitani
-
Patent number: 6468857Abstract: Provided are a semiconductor device in which a MOS transistor of SAC structure and a MOS transistor of salicide structure are provided together, and a method of manufacturing the same. Each gate electrode (3) of gate structures (GT11 to GT13) is covered with an upper nitride film (4) and sidewall nitride film (5). Therefore, when an interlayer insulating film (10) being oxide film is selectively removed for forming contact holes (CH1 and CH2), the upper nitride film (4) and sidewall nitride film (5) are not removed, thereby preventing the gate electrode (3) from being exposed. Particularly, in the gate structures (GT11 and GT12), even when the contact hole (CH1) is dislocated to either side, no short-circuit is developed between a conductor layer (CL1) and the gate electrode (3). Thus, the gate structures (GT11 and GT12) can be disposed without being restricted by the alignment margin of the contact hole (CH1), and the distance between the gates can be reduced for attaining high integration.Type: GrantFiled: August 13, 2001Date of Patent: October 22, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Motoshige Igarashi, Hiroyuki Amishiro, Keiichi Higashitani
-
Publication number: 20020081846Abstract: A method of fabricating a semiconductor device includes following four steps. (1) Cu wiring is buried in an insulating interlayer film, an insulating film for preventing diffusion of copper is deposited on a planarized surface including the Cu wiring as the uppermost layer, and another insulating film having high moisture resistance is deposited. (2) On the insulating film, a photosensitive polyimide material is applied, exposed, and developed, thereby forming an etching mask. (3) The etching mask is cured. (4) By using the cured etching mask, the insulating films are etched to expose the Cu wiring as the uppermost layer.Type: ApplicationFiled: May 9, 2001Publication date: June 27, 2002Inventors: Hideyo Haruhana, Keiichi Higashitani, Hiroyuki Amishiro
-
Patent number: 6383910Abstract: There is described a method of manufacturing a semiconductor device which ensures formation of a step in an alignment mark, to thereby improve the accuracy of alignment. A tungsten layer is formed on an interlayer dielectric film including an opening for use in forming an alignment mark. The tungsten layer is abraded by means of the CMP technique. At this time, the initial thickness of the interlayer dielectric film is made greater than the total sum of the minimum step identifiable for alignment and the amount of abrasion, thus ensuring formation of an alignment step. Further, a gate electrode is removed from the position where a contact alignment mark is formed. Alternatively, an aluminum electrode is removed from a position immediately below a through hole alignment mark.Type: GrantFiled: March 8, 2001Date of Patent: May 7, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Masakazu Okada, Keiichi Higashitani, Hiroyuki Chibahara
-
Publication number: 20020028569Abstract: Provided are a semiconductor device in which a MOS transistor of SAC structure and a MOS transistor of salicide structure are provided together, and a method of manufacturing the same. Each gate electrode (3) of gate structures (GT11 to GT13) is covered with an upper nitride film (4) and sidewall nitride film (5). Therefore, when an interlayer insulating film (10) being oxide film is selectively removed for forming contact holes (CH1 and CH2), the upper nitride film (4) and sidewall nitride film (5) are not removed, thereby preventing the gate electrode (3) from being exposed. Particularly, in the gate structures (GT11 and GT12), even when the contact hole (CH1) is dislocated to either side, no short-circuit is developed between a conductor layer (CL1) and the gate electrode (3). Thus, the gate structures (GT11 and GT12) can be disposed without being restricted by the alignment margin of the contact hole (CH1), and the distance between the gates can be reduced for attaining high integration.Type: ApplicationFiled: August 13, 2001Publication date: March 7, 2002Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Motoshige Igarashi, Hiroyuki Amishiro, Keiichi Higashitani
-
Publication number: 20020025663Abstract: There is described a method of manufacturing a semiconductor device of dual-gate construction, which method prevents occurrence of a highly-resistant local area in a gate electrode of dual-gate construction. A polysilicon layer which is to become a conductive layer of a gate electrode of dual-gate construction is formed on an isolation oxide film. N-type impurities are implanted into an n-type implantation region of the polysilicon film while a photoresist film is taken as a mask. P-type impurities are implanted into a p-type impurity region of the polysilicon film 3 while another photoresist film is taken as a mask. Implantation of n-type impurities and implantation of p-type impurities are performed such that an overlapping area to be doped with these impurities in an overlapping manner is inevitably formed.Type: ApplicationFiled: January 23, 2001Publication date: February 28, 2002Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Kenji Yoshiyama, Keiichi Higashitani, Masao Sugiyama
-
Publication number: 20020016059Abstract: There is described a method of manufacturing a semiconductor device which ensures formation of a step in an alignment mark, to thereby improve the accuracy of alignment. A tungsten layer is formed on an interlayer dielectric film including an opening for use in forming an alignment mark. The tungsten layer is abraded by means of the CMP technique. At this time, the initial thickness of the interlayer dielectric film is made greater than the total sum of the minimum step identifiable for alignment and the amount of abrasion, thus ensuring formation of an alignment step. Further, a gate electrode is removed from the position where a contact alignment mark is formed. Alternatively, an aluminum electrode is removed from a position immediately below a through hole alignment mark.Type: ApplicationFiled: March 8, 2001Publication date: February 7, 2002Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Masakazu Okada, Keiichi Higashitani, Hiroyuki Chibahara
-
Publication number: 20010042892Abstract: A silicon semiconductor substrate has a plurality of active regions having an impurity region and an isolating region which electrically isolates these active regions from each other. The isolating region is formed of a silicon nitride film. A contact hole penetrates an interlayer insulating film and reaches an impurity region. In this semiconductor device, when the contact hole falls across the impurity region and the isolating region, an amount of erosion in the isolating region is reduced.Type: ApplicationFiled: December 10, 1998Publication date: November 22, 2001Inventors: MASAKAZU OKADA, KEIICHI HIGASHITANI, HIROSHI KAWASHIMA
-
Patent number: 6299314Abstract: Provided are a semiconductor device in which a MOS transistor of SAC structure and a MOS transistor of silicide structure are are provided together, and a method of manufacturing the same. Each gate electrode (3) of gate structures (GT11 to GT13) is covered with an upper nitride film (4) and sidewall nitride film (5). Therefore, when an interlayer insulating film (10) being oxide film is selectively removed for forming contact holes (CH1 and CH2), the upper nitride film (4) and sidewall nitride film (5) are not removed, thereby preventing the gate electrode (3) from being exposed. Particularly, in the gate structures (GT11 and GT12), even when the contact hole (CH1) is dislocated to either side, no short-circuit is developed between a conductor layer (CL1) and the gate electrode (3). Thus, the gate structures (GT11 and GT12) can be disposed without being restricted by the alignment margin of the contact hole (CH1), and the distance between the gates can be reduced for attaining high integration.Type: GrantFiled: January 31, 2000Date of Patent: October 9, 2001Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Motoshige Igarashi, Hiroyuki Amishiro, Keiichi Higashitani