Patents by Inventor Keiichi Ohno

Keiichi Ohno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7247902
    Abstract: A semiconductor device comprises a first metal layer, which comprises a buried metal layer connected to a diffusion layer within a substrate or to a lower-layer wiring. A first metal wiring layer, a second metal layer having a buried metal layer, and a second metal wiring layer are sequentially connected. Within a groove passing through insulating layers sandwiching the metal wiring layer from above and below the same as well as on one of the insulating layers there is formed a capacitive element C.
    Type: Grant
    Filed: May 5, 2005
    Date of Patent: July 24, 2007
    Assignee: Sony Corporation
    Inventor: Keiichi Ohno
  • Patent number: 6965139
    Abstract: A semiconductor device has the following construction. A first metal layer consisting of a buried metal layer is connected to a diffusion layer within a substrate or to a lower-layer wiring. Further, a first metal wiring layer, a second metal layer consisting of a buried metal layer, and a second metal wiring layer are sequentially connected. And within a groove passing through insulating layers sandwiching the metal wiring layer from above and below the same as well as on one of the insulating layers there is formed a capacitive element C. When manufacturing the semiconductor device, the second layer-insulating layer is formed in such a way as to cover the metal wiring layer on the first layer-insulating layer. Removal is performed of at least respective parts, corresponding to a memory cell portion, of the first and the second layer-insulating layers. Thereafter, the capacitive element C is formed in regions corresponding to the removed portions of the first and the second layer-insulating layer.
    Type: Grant
    Filed: May 17, 2000
    Date of Patent: November 15, 2005
    Assignee: Sony Corporation
    Inventor: Keiichi Ohno
  • Publication number: 20050205914
    Abstract: A semiconductor device has the following construction. A first metal layer consisting of a buried metal layer is connected to a diffusion layer within a substrate or to a lower-layer wiring. Further, a first metal wiring layer, a second metal layer consisting of a buried metal layer, and a second metal wiring layer are sequentially connected. And within a groove passing through insulating layers sandwiching the metal wiring layer from above and below the same as well as on one of the insulating layers there is formed a capacitive element C. When manufacturing the semiconductor device, the second layer-insulating layer is formed in such a way as to cover the metal wiring layer on the first layer-insulating layer. Removal is performed of at least respective parts, corresponding to a memory cell portion, of the first and the second layer-insulating layers. Thereafter, the capacitive element C is formed in regions corresponding to the removed portions of the first and the second layer-insulating layer.
    Type: Application
    Filed: May 5, 2005
    Publication date: September 22, 2005
    Inventor: Keiichi Ohno
  • Patent number: 6642101
    Abstract: A semiconductor memory device having a high quality storage node electrode preventing for example connection failure between a contact plug and the storage node electrode, including first insulating films formed on a substrate, storage node contact holes formed in the first insulating films, storage node contact plugs buried in the storage node contact holes, a storage node electrode formed connected to the storage node contact plug, and a second insulating film formed above the first insulating film at a gap of the storage node electrode, the storage node electrode and the storage node contact plug being connected at least at part of the top surface and the side surface of the storage node contact plug or the storage node electrode and the second inter-layer insulating film being in contact at least at part of the top surface and the side surface of the second insulating film, and a method for producing the same.
    Type: Grant
    Filed: November 7, 2002
    Date of Patent: November 4, 2003
    Assignee: Sony Corporation
    Inventor: Keiichi Ohno
  • Publication number: 20030071299
    Abstract: A semiconductor memory device having a high quality storage node electrode preventing for example connection failure between a contact plug and the storage node electrode, including first insulating films formed on a substrate, storage node contact holes formed in the first insulating films, storage node contact plugs buried in the storage node contact holes, a storage node electrode formed connected to the storage node contact plug, and a second insulating film formed above the first insulating film at a gap of the storage node electrode, the storage node electrode and the storage node contact plug being connected at least at part of the top surface and the side surface of the storage node contact plug or the storage node electrode and the second inter-layer insulating film being in contact at least at part of the top surface and the side surface of the second insulating film, and a method for producing the same.
    Type: Application
    Filed: November 7, 2002
    Publication date: April 17, 2003
    Inventor: Keiichi Ohno
  • Publication number: 20030052350
    Abstract: A semiconductor device has the following construction. A first metal layer consisting of a buried metal layer is connected to a diffusion layer within a substrate or to a lower-layer wiring. Further, a first metal wiring layer, a second metal layer consisting of a buried metal layer, and a second metal wiring layer are sequentially connected. And within a groove passing through insulating layers sandwiching the metal wiring layer from above and below the same as well as on one of the insulating layers there is formed a capacitive element C.
    Type: Application
    Filed: May 17, 2000
    Publication date: March 20, 2003
    Inventor: Keiichi Ohno
  • Patent number: 6518130
    Abstract: A semiconductor device comprising a plurality of first transistors formed in a first region of a semiconductor substrate and a plurality of second transistors formed in a second region of the semiconductor substrate, wherein each of the first and second transistors has a gate electrode, a channel-forming region and source/drain regions; the gate electrodes constituting the first and second transistors are formed of a polysilicon layer containing an impurity and a silicide layer formed thereon; a silicide layer is formed in the source/drain regions constituting the first transistor; and no silicide layer is formed in the source/drain regions constituting the second transistor.
    Type: Grant
    Filed: September 29, 2000
    Date of Patent: February 11, 2003
    Assignee: Sony Corporation
    Inventor: Keiichi Ohno
  • Patent number: 6501119
    Abstract: A semiconductor memory device having a high quality storage node electrode preventing for example connection failure between a contact plug and the storage node electrode, including first insulating films formed on a substrate, storage node contact holes formed in the first insulating films, storage node contact plugs buried in the storage node contact holes, a storage node electrode formed connected to the storage node contact plug, and a second insulating film formed above the first insulating film at a gap of the storage node electrode, the storage node electrode and the storage node contact plug being connected at least at part of the top surface and the side surface of the storage node contact plug or the storage node electrode and the second inter-layer insulating film being in contact at least at part of the top surface and the side surface of the second insulating film, and a method for producing the same.
    Type: Grant
    Filed: November 23, 1999
    Date of Patent: December 31, 2002
    Assignee: Sony Corporation
    Inventor: Keiichi Ohno
  • Patent number: 6051462
    Abstract: The invention relates to a process for producing a semiconductor device comprising the following steps. A first insulating film and a second insulating film are formed along a shape of the gate electrode on the logic region of the semiconductor substrate. A contact hole is formed in the first and second insulating films in the cell region, and a side wall comprising a material preventing its own silicidation is formed on the inner wall thereof. A conductive material is embedded in the contact hole through a side wall to form a plug, and then the second insulating film is removed to expose the plug and the first insulating film. A spacer side wall is formed on the side wall of the gate electrode in the logic region, and the surface of the semiconductor substrate is exposed, followed by forming a silicide layer thereon. A first interlayer insulating film is formed on the semiconductor substrate, so as to flatten the surface and the upper surface of the plug is exposed.
    Type: Grant
    Filed: August 5, 1998
    Date of Patent: April 18, 2000
    Assignee: Sony Corporation
    Inventor: Keiichi Ohno