Abstract: A multi-core processor system has a processing order manager which manages command blocks in a lock acquired state under exclusive control, an assigner which assigns a command block managed by the processing order manager to one of the processor cores, an exclusion manager which manages command blocks in a lock acquisition waiting state under the exclusive control, and a transfer controller which, when the command block in the lock acquisition waiting state managed by the exclusion manager gets into the lock acquired state, releases the command block from the exclusion manager, and registers the command block in the processing order manager, thereby efficiently processing tasks.

Abstract: An apparatus includes a cache memory for storing user data and control information of the apparatus, a nonvolatile memory and a processor for executing a process including when the power failure occurs, saving the user data and the control information stored in the cache memory into the nonvolatile memory, when the power failure recovers, restoring the data stored in the nonvolatile memory into the cache memory, and erasing the data stored in the nonvolatile memory after restoring the data into the cache memory and when another power failure occurs during erasing the data stored in the nonvolatile memory, erasing the control information stored in the nonvolatile memory if the control information is remained in the nonvolatile memory and saving, into the nonvolatile memory, the updated control information stored in the cache memory and the user data which has been erased from the nonvolatile memory.

Abstract: An apparatus includes a cache memory for storing user data and control information of the apparatus, a nonvolatile memory and a processor for executing a process including when the power failure occurs, saving the user data and the control information stored in the cache memory into the nonvolatile memory, when the power failure recovers, restoring the data stored in the nonvolatile memory into the cache memory, and erasing the data stored in the nonvolatile memory after restoring the data into the cache memory and when another power failure occurs during erasing the data stored in the nonvolatile memory, erasing the control information stored in the nonvolatile memory if the control information is remained in the nonvolatile memory and saving, into the nonvolatile memory, the updated control information stored in the cache memory and the user data which has been erased from the nonvolatile memory.

Abstract: A control device operable under a power supplied from a main power source, the control apparatus includes a memory for storing data with an error detection code, the data being used for execution of processing, a judging section for judging whether an error in the data stored in the memory by the power from a sub power source is detected using the error detection code after the power from the main power source to the memory has been resumed. The control apparatus includes a processing control section for continuing execution of the processing using the data stored in the memory if it has been judged that no error in the data stored in the memory is detected by the judging section, and executing a recovery processing if it has been judged that an error in the data stored in the memory is detected.

Abstract: A storage system accesses a storage device according to the host I/O request and internal I/O request for preventing a time out error of the host I/O due to a stagnation of command processing. The command processing section performs system load management, where the host I/O requests which are not managed by the storage system are managed according to the system load of the storage system, and for the host I/O requests which exceed the system load, the host I/O request is not processed but an error is replied, and the host retries the command to suppress the stagnation of command processing in the system.

Abstract: A storage system accesses a storage device according to the host I/O request and internal I/O request for preventing a time out error of the host I/O due to a stagnation of command processing. The command processing section performs system load management, where the host I/O requests which-are not managed by the storage system are managed according to the system load of the storage system, and for the host I/O requests which exceed the system load, the host I/O request is not processed but an error is replied, and the host retries the command to suppress the stagnation of command processing in the system.