Abstract: Various embodiments include apparatus and methods having circuitry to detect and/or assign identification information to dice arranged in a stack and coupled by conductive paths.

Abstract: Various embodiments include apparatus and methods having circuitry to detect and/or assign identification information to dice arranged in a stack and coupled by conductive paths.

Abstract: Some embodiments include a voltage generator to generate a voltage to apply to a line used to access a memory cell of a memory device in which the voltage is applied to the line when the memory cell is not being accessed, and a power controller to cause the voltage to change between refresh operations of the memory device. Other embodiments including additional apparatus, systems, and methods are described.

Abstract: A memory device includes a command decoder and control interface logic. One or more external inputs, such as row and column address strobes, communicate with the command decoder through the control interface logic. A control signal is also in communication with the control interface logic. During operation of a drowsy mode in the memory device, a self-refresh signal causes the control signal to disable the external inputs. With the external inputs disabled, command hazards are reduced when exiting drowsy mode.

Abstract: Various embodiments include apparatus and methods having circuitry to detect and/or assign identification information to dice arranged in a stack and coupled by conductive paths.

Abstract: Some embodiments include a voltage generator to generate a voltage to apply to a line used to access a memory cell of a memory device in which the voltage is applied to the line when the memory cell is not being accessed, and a power controller to cause the voltage to change between refresh operations of the memory device. Other embodiments including additional apparatus, systems, and methods are described.

Abstract: Some embodiments include a voltage generator to generate a voltage to apply to a line used to access a memory cell of a memory device in which the voltage is applied to the line when the memory cell is not being accessed, and a power controller to cause the voltage to change during a time interval after a refresh operation of the memory device. Other embodiments including additional apparatus, systems, and methods are disclosed.

Abstract: A memory device includes a command decoder and control interface logic. One or more external inputs, such as row and column address strobes, communicate with the command decoder through the control interface logic. A control signal is also in communication with the control interface logic. During operation of a drowsy mode in the memory device, a self-refresh signal causes the control signal to disable the external inputs. With the external inputs disabled, command hazards are reduced when exiting drowsy mode.

Abstract: A memory device includes a command decoder and control interface logic. One or more external inputs, such as row and column address strobes, communicate with the command decoder through the control interface logic. A control signal is also in communication with the control interface logic. During operation of a drowsy mode in the memory device, a self-refresh signal causes the control signal to disable the external inputs. With the external inputs disabled, command hazards are reduced when exiting drowsy mode.

Abstract: A memory device includes a command decoder and control interface logic. One or more external inputs, such as row and column address strobes, communicate with the command decoder through the control interface logic. A control signal is also in communication with the control interface logic. During operation of a drowsy mode in the memory device, a self-refresh signal causes the control signal to disable the external inputs. With the external inputs disabled, command hazards are reduced when exiting drowsy mode.

Abstract: A memory device includes a command decoder and control interface logic. One or more external inputs, such as row and column address strobes, communicate with the command decoder through the control interface logic. A control signal is also in communication with the control interface logic. During operation of a drowsy mode in the memory device, a self-refresh signal causes the control signal to disable the external inputs. With the external inputs disabled, command hazards are reduced when exiting drowsy mode.

Abstract: Some embodiments include a voltage generator to generate a voltage to apply to a line used to access a memory cell of a memory device in which the voltage is applied to the line when the memory cell is not being accessed, and a power controller to cause the voltage to change during a time interval after a refresh operation of the memory device. Other embodiments including additional apparatus, systems, and methods are disclosed.

Abstract: A memory device includes a command decoder and control interface logic. One or more external inputs, such as row and column address strobes, communicate with the command decoder through the control interface logic. A control signal is also in communication with the control interface logic. During operation of a drowsy mode in the memory device, a self-refresh signal causes the control signal to disable the external inputs. With the external inputs disabled, command hazards are reduced when exiting drowsy mode.

Abstract: Some embodiments include a voltage generator to generate a voltage to apply to a line used to access a memory cell of a memory device in which the voltage is applied to the line when the memory cell is not being accessed, and a power controller to cause the voltage to change during a time interval after a refresh operation of the memory device. Other embodiments including additional apparatus, systems, and methods are disclosed.

Abstract: Sense circuits, devices and methods are disclosed, including a sense amplifier circuit that has first and second complementary data lines and a sensing circuit. One of the data lines can be coupled to a memory cell for data sensing and the other data line can be used as reference. The sensing circuit has first and second complementary output nodes and is coupled to the data lines. In a first mode, the sensing circuit can sense a difference between a voltage on the first digit line and a voltage on the second digit line to generate a first voltage differential between the first and second output nodes. In a second mode, the sensing circuit can sense a difference between a current flow in the first digit line and a current flow in the second digit line to generate a second voltage differential between the first and second output nodes. Other sense circuits, devices and methods are also provided.

Abstract: Various embodiments include apparatus and methods having circuitry to detect and/or assign identification information to dice arranged in a stack and coupled by conductive paths.

Abstract: Sense circuits, devices and methods are disclosed, including a sense amplifier circuit that has first and second complementary data lines and a sensing circuit. One of the data lines can be coupled to a memory cell for data sensing and the other data line can be used as reference. The sensing circuit has first and second complementary output nodes and is coupled to the data lines. In a first mode, the sensing circuit can sense a difference between a voltage on the first digit line and a voltage on the second digit line to generate a first voltage differential between the first and second output nodes. In a second mode, the sensing circuit can sense a difference between a current flow in the first digit line and a current flow in the second digit line to generate a second voltage differential between the first and second output nodes. Other sense circuits, devices and methods are also provided.

Abstract: A memory device includes a command decoder and control interface logic. One or more external inputs, such as row and column address strobes, communicate with the command decoder through the control interface logic. A control signal is also in communication with the control interface logic. During operation of a drowsy mode in the memory device, a self-refresh signal causes the control signal to disable the external inputs. With the external inputs disabled, command hazards are reduced when exiting drowsy mode.

Abstract: Sense circuits, devices and methods are disclosed, including a sense amplifier circuit that has first and second complementary data lines and a sensing circuit. One of the data lines can be coupled to a memory cell for data sensing and the other data line can be used as reference. The sensing circuit has first and second complementary output nodes and is coupled to the data lines. In a first mode, the sensing circuit can sense a difference between a voltage on the first digit line and a voltage on the second digit line to generate a first voltage differential between the first and second output nodes. In a second mode, the sensing circuit can sense a difference between a current flow in the first digit line and a current flow in the second digit line to generate a second voltage differential between the first and second output nodes. Other sense circuits, devices and methods are also provided.

Abstract: A memory device includes a command decoder and control interface logic. One or more external inputs, such as row and column address strobes, communicate with the command decoder through the control interface logic. A control signal is also in communication with the control interface logic. During operation of a drowsy mode in the memory device, a self-refresh signal causes the control signal to disable the external inputs. With the external inputs disabled, command hazards are reduced when exiting drowsy mode.