Patents by Inventor Keiichiro MASUKO

Keiichiro MASUKO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11233164
    Abstract: A solar cell (1) includes a semiconductor substrate (10) having a light-receiving surface (10a) and a back surface (10b); an n-type semiconductor layer (13n) and a p-type semiconductor layer (12p) provided on the back surface (10b) of the semiconductor substrate (10), the n-type semiconductor layer (13n) and the p-type semiconductor layer (12p) extending in a first direction and being adjacent to each other in a second direction intersecting with the first direction; and a ground layer (14) provided on the n-type semiconductor layer (13n) and the p-type semiconductor layer (12p). The ground layer (14) includes an n-side ground layer (14n) and a p-side ground layer (14p) separated from each other by a first separating groove (17) having a first separating portion (17a) and a second separating portion (17b) as well as a first bridge portion (18) separating the first separating portion (17a) and the second separating portion (17b).
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: January 25, 2022
    Assignee: PANASONIC CORPORATION
    Inventors: Daiji Kanematsu, Keiichiro Masuko, Izuru Nakai, Hirotaka Katayama
  • Publication number: 20210159355
    Abstract: A solar cell (1) includes a semiconductor substrate (10) having a light-receiving surface (10a) and a back surface (10b); an n-type semiconductor layer (13n) and a p-type semiconductor layer (12p) provided on the back surface (10b) of the semiconductor substrate (10), the n-type semiconductor layer (13n) and the p-type semiconductor layer (12p) extending in a first direction and being adjacent to each other in a second direction intersecting with the first direction; and a ground layer (14) provided on the n-type semiconductor layer (13n) and the p-type semiconductor layer (12p). The ground layer (14) includes an n-side ground layer (14n) and a p-side ground layer (14p) separated from each other by a first separating groove (17) having a first separating portion (17a) and a second separating portion (17b) as well as a first bridge portion (18) separating the first separating portion (17a) and the second separating portion (17b).
    Type: Application
    Filed: January 9, 2019
    Publication date: May 27, 2021
    Inventors: Daiji KANEMATSU, Keiichiro MASUKO, Izuru NAKAI, Hirotaka KATAYAMA
  • Patent number: 10672931
    Abstract: A solar cell is equipped with: a wafer; an n-type laminated body that is provided on the first main surface side of the wafer; and a p-type laminated body, which is provided on the first main surface side of the wafer such that the p-type laminated body is adjacent to the n-type laminated body in the X direction, and which extends in the Y direction. The wafer has: a lightly doped region that is doped to be n type; and a plurality of first main surface-side highly doped regions, which have an n-type dopant concentration that is higher than that of the lightly doped region, and which are provided between the lightly doped region and the p-type laminated body. The first main surface-side highly doped regions are discretely provided at intervals in the Y direction.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: June 2, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Keiichiro Masuko, Wataru Shinohara
  • Patent number: 10546969
    Abstract: A solar cell is provided that comprising a semiconductor substrate having a first conductivity type; a first semiconductor layer having the first conductivity type, and on a principal surface of the semiconductor substrate; an insulation layer on the first semiconductor layer; a protective layer on the insulation layer; and a second semiconductor layer having a second conductivity type, and on the semiconductor substrate and the protective layer. A recessed region is positioned at a lateral side of the insulation layer, the recessed region formed by recessing a side surface of the insulation layer inward from a side surface of the first semiconductor layer and a side surface of the protective layer, and the second semiconductor layer is positioned in the recessed region above the first semiconductor layer in the recessed region.
    Type: Grant
    Filed: May 21, 2015
    Date of Patent: January 28, 2020
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Naofumi Hayashi, Takahiro Mishima, Keiichiro Masuko
  • Patent number: 10483429
    Abstract: A method of manufacturing a solar cell includes: providing an insulating layer on a semiconductor layer provided on at least a part of a principle surface of a semiconductor substrate; providing a mask layer on the insulating layer; removing a part of the mask layer by laser irradiation so as to form a first opening through which the insulating layer is exposed; and removing, by an etching agent, the insulating layer exposed through the first opening so as to form a second opening through which the semiconductor layer is exposed.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: November 19, 2019
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventor: Keiichiro Masuko
  • Patent number: 10475946
    Abstract: A method of manufacturing a solar cell includes: forming a conductive thin film layer on a semiconductor substrate; forming an insulating film on the conductive thin film layer; forming a conductive thin film layer exposed portion by removing a part of the insulating film; forming a plating film in the conductive thin film layer exposed portion; and removing the insulating film and the conductive thin film layer in an area not overlapping the plating film, wherein the plating film formed in the forming of a plating film is formed to cover the insulating film.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: November 12, 2019
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Keiichiro Masuko, Yasufumi Tsunomura
  • Publication number: 20190305152
    Abstract: A solar cell module includes: a first solar cell having a first principal surface on which n-side and p-side electrodes are provided; a second solar cell having a second principal surface on which n-side and p-side electrodes are provided; a connection member that connects the first principal surface and the second principal surface; a first conductive adhesion part that connects the n-side electrode of the first solar cell with the connection member; a second conductive adhesion part that connects the p-side electrode of the second solar cell with the connection member; and an intermediate insulation part that is provided at a position on a surface of the connection member between the first conductive adhesion part and the second conductive adhesion part and is provided at a distance from at least one of the first solar cell and the second solar cell.
    Type: Application
    Filed: June 14, 2019
    Publication date: October 3, 2019
    Inventor: Keiichiro MASUKO
  • Publication number: 20190245108
    Abstract: A method of manufacturing a solar cell includes: forming a conductive thin film layer on a semiconductor substrate; forming an insulating film on the conductive thin film layer; forming a conductive thin film layer exposed portion by removing a part of the insulating film; forming a plating film in the conductive thin film layer exposed portion; and removing the insulating film and the conductive thin film layer in an area not overlapping the plating film, wherein the plating film formed in the forming of a plating film is formed to cover the insulating film.
    Type: Application
    Filed: April 16, 2019
    Publication date: August 8, 2019
    Inventors: Keiichiro MASUKO, Yasufumi TSUNOMURA
  • Publication number: 20190221702
    Abstract: In an example embodiment, a method for producing a solar cell includes forming a passivation layer over a first principal surface of a crystalline silicon wafer; forming a substantially intrinsic i-type silicon layer over the passivation layer; forming n+ layers on and near principal surfaces of the wafer and turning the i-type silicon layer to be an n-type crystalline silicon layer by thermally diffusing an n-type dopant in the passivation layer, the i-type silicon layer, and the crystalline silicon wafer; and forming a p-type amorphous silicon layer on a second principal surface side of the crystalline silicon wafer in which the n+ layers are formed (n-type crystalline silicon wafer).
    Type: Application
    Filed: March 21, 2019
    Publication date: July 18, 2019
    Applicant: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Kazunori Fujita, Keiichiro Masuko, Ayumu Yano
  • Publication number: 20190207052
    Abstract: A method of manufacturing a solar cell includes: forming a p-type surface and an n-type surface on the back surface of a photoelectric conversion unit; forming a base layer and a conductive layer above the p-type surface and the n-type surface; forming a resist film on the conductive layer, in a region corresponding to a separating groove; forming an n-side conductive layer and a p-side conductive layer and an n-side tin (Sn) layer and p-side Sn layer which include tin in stated order, by electroplating using, as a seed layer, the conductive layer on which the resist film is formed; forming an n-side metal layer and a p-side metal layer, which are alloyed with the n-side Sn layer and the p-side Sn layer, respectively, on the n-side Sn layer and the p-side Sn layer, respectively; and etching each of the conductive layer and the base layer.
    Type: Application
    Filed: December 19, 2018
    Publication date: July 4, 2019
    Inventors: Keiichiro MASUKO, Youhei MURAKAMI, Koichi HIRANO
  • Patent number: 10312396
    Abstract: A method of manufacturing a solar cell includes: forming a conductive thin film layer on a semiconductor substrate; forming an insulating film on the conductive thin film layer; forming a conductive thin film layer exposed portion by removing a part of the insulating film; forming a plating film in the conductive thin film layer exposed portion; and removing the insulating film and the conductive thin film layer in an area not overlapping the plating film, wherein the plating film formed in the forming of a plating film is formed to cover the insulating film.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: June 4, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Keiichiro Masuko, Yasufumi Tsunomura
  • Publication number: 20190027637
    Abstract: In a backside-junction type solar cell, polycrystalline silicon grains including at least one of amorphous silicon microcrystalline silicon, and polycrystalline silicon exist discretely over a passivation layer and a second conductivity type layer.
    Type: Application
    Filed: September 27, 2018
    Publication date: January 24, 2019
    Applicant: Panasonic Intellectual Property Management Co., Lt d.
    Inventors: Hirotaka Katayama, Wataru Shinohara, Keiichiro Masuko
  • Publication number: 20190027630
    Abstract: A solar cell is equipped with: a wafer; an n-type laminated body that is provided on the first main surface side of the wafer; and a p-type laminated body, which is provided on the first main surface side of the wafer such that the p-type laminated body is adjacent to the n-type laminated body in the X direction, and which extends in the Y direction. The wafer has: a lightly doped region that is doped to be n type; and a plurality of first main surface-side highly doped regions, which have an n-type dopant concentration that is higher than that of the lightly doped region, and which are provided between the lightly doped region and the p-type laminated body. The first main surface-side highly doped regions are discretely provided at intervals in the Y direction.
    Type: Application
    Filed: September 27, 2018
    Publication date: January 24, 2019
    Applicant: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Keiichiro Masuko, Wataru Shinohara
  • Publication number: 20190006534
    Abstract: According to one example of an embodiment of the present invention, a solar cell is provided with an n-type crystalline silicon wafer; a first passivation layer, which is formed on the light receiving surface of the n-type crystalline silicon wafer, and which is configured by having, as a main component, silicon oxide, silicon carbide, or silicon nitride; an n-type crystalline silicon layer formed on the first passivation layer; a second passivation layer formed on the rear surface of the n-type crystalline silicon wafer; and a p-type amorphous silicon layer formed on the second passivation layer.
    Type: Application
    Filed: August 13, 2018
    Publication date: January 3, 2019
    Applicant: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Kazunori Fujita, Daisuke Fujishima, Yasufumi Tsunomura, Mikio Taguchi, Keiichiro Masuko
  • Publication number: 20180219116
    Abstract: A solar cell module includes a plurality of solar cells. A plurality of finger electrodes for a first electrode are provided on a principal surface of a semiconductor substrate of the solar cell. A bus bar electrode for the first electrode is provided on the principal surface of the semiconductor substrate and is connected to the plurality of finger electrodes for the first electrode. The bus bar electrode for the first electrode extends beyond the semiconductor substrate toward an adjacent further solar cell. A portion of the bus bar electrode for the first electrode provided on the principal surface of the semiconductor substrate and a portion of the bus bar electrode for the first electrode extending beyond the semiconductor substrate are formed to be integrated with each other.
    Type: Application
    Filed: March 27, 2018
    Publication date: August 2, 2018
    Inventor: Keiichiro Masuko
  • Publication number: 20180219107
    Abstract: A semiconductor substrate has a first area and a second area. A seed layer is provided on a principal surface of the semiconductor substrate including the first area and the second area. Insulating layers are discretely provided on the seed layer in the first area and not provided on the seed layer in the second area. Plating layers in the first area are connected to the seed layer between the discretely provided insulating layers and connected to the seed layer in the second area.
    Type: Application
    Filed: March 26, 2018
    Publication date: August 2, 2018
    Inventor: Keiichiro MASUKO
  • Publication number: 20180219119
    Abstract: A method of manufacturing a solar cell includes: forming a conductive thin film layer on a semiconductor substrate; forming an insulating film on the conductive thin film layer; forming a conductive thin film layer exposed portion by removing a part of the insulating film; forming a plating film in the conductive thin film layer exposed portion; and removing the insulating film and the conductive thin film layer in an area not overlapping the plating film, wherein the plating film formed in the forming of a plating film is formed to cover the insulating film.
    Type: Application
    Filed: March 28, 2018
    Publication date: August 2, 2018
    Inventors: Keiichiro MASUKO, Yasufumi TSUNOMURA
  • Patent number: D828292
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: September 11, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Naoki Yoshimura, Keiichiro Masuko, Daisuke Fujishima, Masato Shigematsu
  • Patent number: D894823
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: September 1, 2020
    Assignee: PANASONIC INTELLECTUAL PROPETY MANAGEMENT CO., LTD.
    Inventors: Naoki Yoshimura, Keiichiro Masuko, Daisuke Fujishima, Masato Shigematsu
  • Patent number: D894824
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: September 1, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Naoki Yoshimura, Keiichiro Masuko, Daisuke Fujishima, Masato Shigematsu