Patents by Inventor Keiichiro MASUKO
Keiichiro MASUKO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11233164Abstract: A solar cell (1) includes a semiconductor substrate (10) having a light-receiving surface (10a) and a back surface (10b); an n-type semiconductor layer (13n) and a p-type semiconductor layer (12p) provided on the back surface (10b) of the semiconductor substrate (10), the n-type semiconductor layer (13n) and the p-type semiconductor layer (12p) extending in a first direction and being adjacent to each other in a second direction intersecting with the first direction; and a ground layer (14) provided on the n-type semiconductor layer (13n) and the p-type semiconductor layer (12p). The ground layer (14) includes an n-side ground layer (14n) and a p-side ground layer (14p) separated from each other by a first separating groove (17) having a first separating portion (17a) and a second separating portion (17b) as well as a first bridge portion (18) separating the first separating portion (17a) and the second separating portion (17b).Type: GrantFiled: January 9, 2019Date of Patent: January 25, 2022Assignee: PANASONIC CORPORATIONInventors: Daiji Kanematsu, Keiichiro Masuko, Izuru Nakai, Hirotaka Katayama
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Publication number: 20210159355Abstract: A solar cell (1) includes a semiconductor substrate (10) having a light-receiving surface (10a) and a back surface (10b); an n-type semiconductor layer (13n) and a p-type semiconductor layer (12p) provided on the back surface (10b) of the semiconductor substrate (10), the n-type semiconductor layer (13n) and the p-type semiconductor layer (12p) extending in a first direction and being adjacent to each other in a second direction intersecting with the first direction; and a ground layer (14) provided on the n-type semiconductor layer (13n) and the p-type semiconductor layer (12p). The ground layer (14) includes an n-side ground layer (14n) and a p-side ground layer (14p) separated from each other by a first separating groove (17) having a first separating portion (17a) and a second separating portion (17b) as well as a first bridge portion (18) separating the first separating portion (17a) and the second separating portion (17b).Type: ApplicationFiled: January 9, 2019Publication date: May 27, 2021Inventors: Daiji KANEMATSU, Keiichiro MASUKO, Izuru NAKAI, Hirotaka KATAYAMA
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Patent number: 10672931Abstract: A solar cell is equipped with: a wafer; an n-type laminated body that is provided on the first main surface side of the wafer; and a p-type laminated body, which is provided on the first main surface side of the wafer such that the p-type laminated body is adjacent to the n-type laminated body in the X direction, and which extends in the Y direction. The wafer has: a lightly doped region that is doped to be n type; and a plurality of first main surface-side highly doped regions, which have an n-type dopant concentration that is higher than that of the lightly doped region, and which are provided between the lightly doped region and the p-type laminated body. The first main surface-side highly doped regions are discretely provided at intervals in the Y direction.Type: GrantFiled: September 27, 2018Date of Patent: June 2, 2020Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Keiichiro Masuko, Wataru Shinohara
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Patent number: 10546969Abstract: A solar cell is provided that comprising a semiconductor substrate having a first conductivity type; a first semiconductor layer having the first conductivity type, and on a principal surface of the semiconductor substrate; an insulation layer on the first semiconductor layer; a protective layer on the insulation layer; and a second semiconductor layer having a second conductivity type, and on the semiconductor substrate and the protective layer. A recessed region is positioned at a lateral side of the insulation layer, the recessed region formed by recessing a side surface of the insulation layer inward from a side surface of the first semiconductor layer and a side surface of the protective layer, and the second semiconductor layer is positioned in the recessed region above the first semiconductor layer in the recessed region.Type: GrantFiled: May 21, 2015Date of Patent: January 28, 2020Assignee: Panasonic Intellectual Property Management Co., Ltd.Inventors: Naofumi Hayashi, Takahiro Mishima, Keiichiro Masuko
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Patent number: 10483429Abstract: A method of manufacturing a solar cell includes: providing an insulating layer on a semiconductor layer provided on at least a part of a principle surface of a semiconductor substrate; providing a mask layer on the insulating layer; removing a part of the mask layer by laser irradiation so as to form a first opening through which the insulating layer is exposed; and removing, by an etching agent, the insulating layer exposed through the first opening so as to form a second opening through which the semiconductor layer is exposed.Type: GrantFiled: September 22, 2017Date of Patent: November 19, 2019Assignee: Panasonic Intellectual Property Management Co., Ltd.Inventor: Keiichiro Masuko
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Patent number: 10475946Abstract: A method of manufacturing a solar cell includes: forming a conductive thin film layer on a semiconductor substrate; forming an insulating film on the conductive thin film layer; forming a conductive thin film layer exposed portion by removing a part of the insulating film; forming a plating film in the conductive thin film layer exposed portion; and removing the insulating film and the conductive thin film layer in an area not overlapping the plating film, wherein the plating film formed in the forming of a plating film is formed to cover the insulating film.Type: GrantFiled: April 16, 2019Date of Patent: November 12, 2019Assignee: Panasonic Intellectual Property Management Co., Ltd.Inventors: Keiichiro Masuko, Yasufumi Tsunomura
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Publication number: 20190305152Abstract: A solar cell module includes: a first solar cell having a first principal surface on which n-side and p-side electrodes are provided; a second solar cell having a second principal surface on which n-side and p-side electrodes are provided; a connection member that connects the first principal surface and the second principal surface; a first conductive adhesion part that connects the n-side electrode of the first solar cell with the connection member; a second conductive adhesion part that connects the p-side electrode of the second solar cell with the connection member; and an intermediate insulation part that is provided at a position on a surface of the connection member between the first conductive adhesion part and the second conductive adhesion part and is provided at a distance from at least one of the first solar cell and the second solar cell.Type: ApplicationFiled: June 14, 2019Publication date: October 3, 2019Inventor: Keiichiro MASUKO
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Publication number: 20190245108Abstract: A method of manufacturing a solar cell includes: forming a conductive thin film layer on a semiconductor substrate; forming an insulating film on the conductive thin film layer; forming a conductive thin film layer exposed portion by removing a part of the insulating film; forming a plating film in the conductive thin film layer exposed portion; and removing the insulating film and the conductive thin film layer in an area not overlapping the plating film, wherein the plating film formed in the forming of a plating film is formed to cover the insulating film.Type: ApplicationFiled: April 16, 2019Publication date: August 8, 2019Inventors: Keiichiro MASUKO, Yasufumi TSUNOMURA
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Publication number: 20190221702Abstract: In an example embodiment, a method for producing a solar cell includes forming a passivation layer over a first principal surface of a crystalline silicon wafer; forming a substantially intrinsic i-type silicon layer over the passivation layer; forming n+ layers on and near principal surfaces of the wafer and turning the i-type silicon layer to be an n-type crystalline silicon layer by thermally diffusing an n-type dopant in the passivation layer, the i-type silicon layer, and the crystalline silicon wafer; and forming a p-type amorphous silicon layer on a second principal surface side of the crystalline silicon wafer in which the n+ layers are formed (n-type crystalline silicon wafer).Type: ApplicationFiled: March 21, 2019Publication date: July 18, 2019Applicant: Panasonic Intellectual Property Management Co., Ltd.Inventors: Kazunori Fujita, Keiichiro Masuko, Ayumu Yano
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Publication number: 20190207052Abstract: A method of manufacturing a solar cell includes: forming a p-type surface and an n-type surface on the back surface of a photoelectric conversion unit; forming a base layer and a conductive layer above the p-type surface and the n-type surface; forming a resist film on the conductive layer, in a region corresponding to a separating groove; forming an n-side conductive layer and a p-side conductive layer and an n-side tin (Sn) layer and p-side Sn layer which include tin in stated order, by electroplating using, as a seed layer, the conductive layer on which the resist film is formed; forming an n-side metal layer and a p-side metal layer, which are alloyed with the n-side Sn layer and the p-side Sn layer, respectively, on the n-side Sn layer and the p-side Sn layer, respectively; and etching each of the conductive layer and the base layer.Type: ApplicationFiled: December 19, 2018Publication date: July 4, 2019Inventors: Keiichiro MASUKO, Youhei MURAKAMI, Koichi HIRANO
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Patent number: 10312396Abstract: A method of manufacturing a solar cell includes: forming a conductive thin film layer on a semiconductor substrate; forming an insulating film on the conductive thin film layer; forming a conductive thin film layer exposed portion by removing a part of the insulating film; forming a plating film in the conductive thin film layer exposed portion; and removing the insulating film and the conductive thin film layer in an area not overlapping the plating film, wherein the plating film formed in the forming of a plating film is formed to cover the insulating film.Type: GrantFiled: March 28, 2018Date of Patent: June 4, 2019Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Keiichiro Masuko, Yasufumi Tsunomura
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Publication number: 20190027637Abstract: In a backside-junction type solar cell, polycrystalline silicon grains including at least one of amorphous silicon microcrystalline silicon, and polycrystalline silicon exist discretely over a passivation layer and a second conductivity type layer.Type: ApplicationFiled: September 27, 2018Publication date: January 24, 2019Applicant: Panasonic Intellectual Property Management Co., Lt d.Inventors: Hirotaka Katayama, Wataru Shinohara, Keiichiro Masuko
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Publication number: 20190027630Abstract: A solar cell is equipped with: a wafer; an n-type laminated body that is provided on the first main surface side of the wafer; and a p-type laminated body, which is provided on the first main surface side of the wafer such that the p-type laminated body is adjacent to the n-type laminated body in the X direction, and which extends in the Y direction. The wafer has: a lightly doped region that is doped to be n type; and a plurality of first main surface-side highly doped regions, which have an n-type dopant concentration that is higher than that of the lightly doped region, and which are provided between the lightly doped region and the p-type laminated body. The first main surface-side highly doped regions are discretely provided at intervals in the Y direction.Type: ApplicationFiled: September 27, 2018Publication date: January 24, 2019Applicant: Panasonic Intellectual Property Management Co., Ltd.Inventors: Keiichiro Masuko, Wataru Shinohara
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Publication number: 20190006534Abstract: According to one example of an embodiment of the present invention, a solar cell is provided with an n-type crystalline silicon wafer; a first passivation layer, which is formed on the light receiving surface of the n-type crystalline silicon wafer, and which is configured by having, as a main component, silicon oxide, silicon carbide, or silicon nitride; an n-type crystalline silicon layer formed on the first passivation layer; a second passivation layer formed on the rear surface of the n-type crystalline silicon wafer; and a p-type amorphous silicon layer formed on the second passivation layer.Type: ApplicationFiled: August 13, 2018Publication date: January 3, 2019Applicant: Panasonic Intellectual Property Management Co., Ltd.Inventors: Kazunori Fujita, Daisuke Fujishima, Yasufumi Tsunomura, Mikio Taguchi, Keiichiro Masuko
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Publication number: 20180219116Abstract: A solar cell module includes a plurality of solar cells. A plurality of finger electrodes for a first electrode are provided on a principal surface of a semiconductor substrate of the solar cell. A bus bar electrode for the first electrode is provided on the principal surface of the semiconductor substrate and is connected to the plurality of finger electrodes for the first electrode. The bus bar electrode for the first electrode extends beyond the semiconductor substrate toward an adjacent further solar cell. A portion of the bus bar electrode for the first electrode provided on the principal surface of the semiconductor substrate and a portion of the bus bar electrode for the first electrode extending beyond the semiconductor substrate are formed to be integrated with each other.Type: ApplicationFiled: March 27, 2018Publication date: August 2, 2018Inventor: Keiichiro Masuko
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Publication number: 20180219107Abstract: A semiconductor substrate has a first area and a second area. A seed layer is provided on a principal surface of the semiconductor substrate including the first area and the second area. Insulating layers are discretely provided on the seed layer in the first area and not provided on the seed layer in the second area. Plating layers in the first area are connected to the seed layer between the discretely provided insulating layers and connected to the seed layer in the second area.Type: ApplicationFiled: March 26, 2018Publication date: August 2, 2018Inventor: Keiichiro MASUKO
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Publication number: 20180219119Abstract: A method of manufacturing a solar cell includes: forming a conductive thin film layer on a semiconductor substrate; forming an insulating film on the conductive thin film layer; forming a conductive thin film layer exposed portion by removing a part of the insulating film; forming a plating film in the conductive thin film layer exposed portion; and removing the insulating film and the conductive thin film layer in an area not overlapping the plating film, wherein the plating film formed in the forming of a plating film is formed to cover the insulating film.Type: ApplicationFiled: March 28, 2018Publication date: August 2, 2018Inventors: Keiichiro MASUKO, Yasufumi TSUNOMURA
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Patent number: D828292Type: GrantFiled: December 20, 2016Date of Patent: September 11, 2018Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Naoki Yoshimura, Keiichiro Masuko, Daisuke Fujishima, Masato Shigematsu
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Patent number: D894823Type: GrantFiled: July 31, 2018Date of Patent: September 1, 2020Assignee: PANASONIC INTELLECTUAL PROPETY MANAGEMENT CO., LTD.Inventors: Naoki Yoshimura, Keiichiro Masuko, Daisuke Fujishima, Masato Shigematsu
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Patent number: D894824Type: GrantFiled: July 31, 2018Date of Patent: September 1, 2020Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Naoki Yoshimura, Keiichiro Masuko, Daisuke Fujishima, Masato Shigematsu