Abstract: An add/drop multiplexer where a first signal converter converts first-low-order-group signals received from DSn network, into high-order-group signals, which are transferred to SDH (SONET) network and to which second-low-order-group signals, slower in transmission speed than the first-low-order-group signals are added. A second signal converter converts high-order-group signals, received from SDH (SONET) network, into first-low-order-group signals. A selector selectively outputs first-low-order-group signals received from the DSn network, or first-low-order-group signals obtained by the second signal converter, as the input signals to the first signal converter.

Abstract: An ADM apparatus includes a first synchronism section for detecting synchronism when a reception frame received from a reception port is a first frame, a fault information detection section for detecting whether or not fault information is set in a first predetermined region of an overhead of the first frame and outputting a signal representative of whether or not the fault information is set, a second synchronism section for detecting synchronism when the reception frame is a second frame, a third synchronism section for detecting synchronism when the reception frame is a third frame accommodated in the second frame, and an inhibit section for invalidating the output signal of the fault information detection section if, when the synchronism is detected by the first and second synchronism sections, synchronism is detected with regard to the preceding frame by the second synchronism section.

Abstract: A distributed power supply is incorporated in a device including a plurality of PCB. An on-board power supply is provided in the distributed power supply. The on-board power supply individually supplies a secondary power to each PCB using a primary power. Each PCB includes a primary power supply monitoring circuit, a PCB internal power supply monitoring circuit, and a pulse generation circuit. The primary power supply circuit detects an abnormality in the voltage of in the primary power supplied to the on-board power supply. The PCB internal power supply monitoring circuit restarts the PCB when the abnormality is detected. The pulse generation circuit transmits a restart signal to the other PCBs in the device.

Abstract: A distributed power supply is incorporated in a device including a plurality of PCB. An on-board power supply is provided in the distributed power supply. The on-board power supply individually supplies a secondary power to each PCB using a primary power. Each PCB includes a primary power supply monitoring circuit, a PCB internal power supply monitoring circuit, and a pulse generation circuit. The primary power supply circuit detects an abnormality in the voltage of in the primary power supplied to the on-board power supply. The PCB internal power supply monitoring circuit restarts the PCB when the abnormality is detected. The pulse generation circuit transmits a restart signal to the other PCBs in the device.

Abstract: After a DS3 signal is terminated by the DS3 interface circuit, an ATM cell is extracted by an ATM cell extraction circuit from a signal input through a DS3 network after performing an ATM mapping process. The ATM cell is mapped in a SONET frame by an ATM cell/N.A. new synchronous SONET STS mapping unit, and is transmitted to a SONET. When an STS signal is input from the SONET, an STS frame is terminated in an STS demapping circuit. An ATM cell is extracted by an ATM cell extraction circuit, and is mapped in the DS3 signal and transmitted by an ATM cell/N.A. asynchronous DS3 mapping unit.

Abstract: After a DS3 signal is terminated by the DS3 interface circuit, an ATM cell is extracted by an ATM cell extraction circuit from a signal input through a DS3 network after performing an ATM mapping process. The ATM cell is mapped in a SONET frame by an ATM cell/N.A. new synchronous SONET STS mapping unit, and is transmitted to a SONET. When an STS signal is input from the SONET, an STS frame is terminated in an STS demapping circuit. An ATM cell is extracted by an ATM cell extraction circuit, and is mapped in the DS3 signal and transmitted by an ATM cell/N.A. asynchronous DS3 mapping unit.

Abstract: An ADM apparatus includes a first synchronism section for detecting synchronism when a reception frame received from a reception port is a first frame, a fault information detection section for detecting whether or not fault information is set in a first predetermined region of an overhead of the first frame and outputting a signal representative of whether or not the fault information is set, a second synchronism section for detecting synchronism when the reception frame is a second frame, a third synchronism section for detecting synchronism when the reception frame is a third frame accommodated in the second frame, and an inhibit section for invalidating the output signal of the fault information detection section if, when the synchronism is detected by the first and second synchronism sections, synchronism is detected with regard to the preceding frame by the second synchronism section.

Abstract: A signal loopback device including a multiplexing/demultiplexing unit to carry out multiplexing/demultiplexing between a DS3 signal serving as a digital signal conforming to a DS3 C-bit parity system and a DS1 signal, a DS1 signal loopback storage unit to return the DS1 signal, a DS3 signal loopback storage unit to return the DS3 signal in an original input signal format, a selecting unit to select any one of DS3 loopback signals from the multiplexing/demultiplexing unit and the DS3 signal loopback storage unit, a protected detecting unit to output, when detecting loopback execution/cancellation information a plurality of times, a result of detection showing that loopback is to be executed or canceled, and a loopback control unit to make a control for loopback execution or loopback cancellation to the DS1 signal loopback storage unit, the DS3 signal loopback storage unit, and the selecting unit depending upon the result of detection.

Abstract: An add/drop multiplexer where a first signal converter converts first-low-order-group signals received from DSn network, into high-order-group signals, which are transferred to SDH (SONET) network and to which second-low-order-group signals, slower in transmission speed than the first-low-order-group signals are added. A second signal converter converts high-order-group signals, received from SDH (SONET) network, into first-low-order-group signals. A selector selectively outputs first-low-order-group signals received from the DSn network, or first-low-order-group signals obtained by the second signal converter, as the input signals to the first signal converter.

Abstract: A transmitter having an interface module to serve as an interface between ATM cells and synchronous frames. The interface module comprises a plurality of first physical paths for inputting ATM cells with channel identifiers given thereto to identify channels respectively; a second physical path for outputting a synchronous frame signal; a channel identifier inserter for inserting the channel identifiers, which are given to the first physical paths where the ATM cells are inputted, into predetermined areas of the ATM cells; and a mapper for mapping the multi-channel ATM cells with the channel identifiers inserted therein to one synchronous frame signal and outputting the same to the second physical path.

Abstract: A transmission apparatus includes a shelf which includes a working card slot and a protection card slot, the working card slot supplying a first slot ID to a first card inserted in the working card slot, and the protection card slot supplying a second slot ID to a second card inserted in the protection card slot. A control logic circuit, provided within each of the first and second cards, receives one of the first slot ID or the second slot ID, a redundancy/non-redundancy R/N signal and a working/protection W/P signal, and outputs a control signal depending on the related slot ID, the R/N signal and the W/P signal. A line connection relay, provided within each of the first and second cards, connects either a working line or a protection line to an output of the related card in accordance with the control signal supplied by the control logic circuit.

Abstract: Conventionally, since in an ADM apparatus being an interface apparatus between a DS3 network and a SONET network a DS3 frame is mapped into an STS1 frame, the multiplexing and demultiplexing of the STS1 frame has to be carried out in units of DS3 frames. For this reason, the DS3 frame is demultiplexed and converted to a DS2 frame, and then to a DS1 frame, the DS1 frame is multiplexed and converted to a VT1.5 frame, and this VT1.5 frame is mapped into an STS1 frame. Since the VT1.5 frame is synchronized with the STS1 frame, the multiplexing and demultiplexing processes can be carried out in smaller units of the VT1.5 frame. Accordingly, data can be distributed on smaller units on a network.