Patents by Inventor Keiji Jono

Keiji Jono has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory cell with trench-isolated transistor including first and second isolation trenches
    Patent number: 7268402
    Abstract: An isolation trench in a semiconductor includes a first isolation trench portion having a first depth and having a first sidewall intersecting a surface of the semiconductor at a first angle. A second isolation trench portion extends within and below the first isolation trench portion. The second isolation trench portion has a second depth and includes a second sidewall. The second sidewall intersects the first sidewall at an angle with respect to the surface that is greater than the first angle. A dielectric material fills the first and second isolation trench portions.
    Type: Grant
    Filed: April 29, 2005
    Date of Patent: September 11, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Keiji Jono, Hirokazu Ueda, Hiroyuki Watanabe
  • Memory cells
    Publication number: 20050202648
    Abstract: An isolation trench in a semiconductor includes a first isolation trench portion having a first depth and having a first sidewall intersecting a surface of the semiconductor at a first angle. A second isolation trench portion extends within and below the first isolation trench portion. The second isolation trench portion has a second depth and includes a second sidewall. The second sidewall intersects the first sidewall at an angle with respect to the surface that is greater than the first angle. A dielectric material fills the first and second isolation trench portions.
    Type: Application
    Filed: April 29, 2005
    Publication date: September 15, 2005
    Inventors: Keiji Jono, Hirokazu Ueda, Hiroyuki Watanabe
  • Trench isolated transistors, trench isolation structures, memory cells, and DRAMs
    Patent number: 6894354
    Abstract: An isolation trench in a semiconductor includes a first isolation trench portion having a first depth and having a first sidewall intersecting a surface of the semiconductor at a first angle. A second isolation trench portion extends within and below the first isolation trench portion. The second isolation trench portion has a second depth and includes a second sidewall. The second sidewall intersects the first sidewall at an angle with respect to the surface that is greater than the first angle. A dielectric material fills the first and second isolation trench portions.
    Type: Grant
    Filed: November 8, 2001
    Date of Patent: May 17, 2005
    Assignees: Micron Technology, Inc., KMT Semiconductor, LTD
    Inventors: Keiji Jono, Hirokazu Ueda, Hiroyuki Watanabe
  • METHODS OF FORMING AN ISOLATION TRENCH IN A SEMICONDUCTOR, METHODS OF FORMING AN ISOLATION TRENCH IN A SURFACE OF A SILICON WAFER, METHODS OF FORMING AN ISOLATION TRENCH-ISOLATED TRANSISTOR, TRENCH-ISOLATED TRANSISTOR, TRENCH ISOLATION STRUCTURES FORMED IN A SEMICONDUCTOR, MEMORY CELLS AND DRAMS
    Patent number: 6830977
    Abstract: A method of forming an isolation trench in a semiconductor includes forming a first isolation trench portion having a first depth and having a first sidewall intersecting a surface of the semiconductor at a first angle. The method also includes forming a second isolation trench portion within and extending below the first isolation trench portion. The second isolation trench portion has a second depth and includes a second sidewall. The second sidewall intersects the first sidewall at an angle with respect to the surface that is greater than the first angle. A dielectric material fills the first and second isolation trench portions.
    Type: Grant
    Filed: August 31, 2000
    Date of Patent: December 14, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Keiji Jono, Hirokazu Ueda, Hiroyuki Watanabe
  • Methods of forming an isolation trench in a semiconductor, methods of forming an isolation trench in a surface of a silicon wafer, methods of forming an isolation trench-isolated transistor, trench-isolated transistor, trench isolation structures formed in a semiconductor, memory cells and DRAMs
    Publication number: 20020121673
    Abstract: A method of forming an isolation trench in a semiconductor includes forming a first isolation trench portion having a first depth and having a first sidewall intersecting a surface of the semiconductor at a first angle. The method also includes forming a second isolation trench portion within and extending below the first isolation trench portion. The second isolation trench portion has a second depth and includes a second sidewall. The second sidewall intersects the first sidewall at an angle with respect to the surface that is greater than the first angle. A dielectric material fills the first and second isolation trench portions.
    Type: Application
    Filed: November 8, 2001
    Publication date: September 5, 2002
    Inventors: Keiji Jono, Hirokazu Ueda, Hiroyuki Watanabe