Patents by Inventor Keijiro Uehara

Keijiro Uehara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6342710
    Abstract: A semiconductor integrated circuit, particularly a circuit for a high-speed low-power-consumption table look-aside buffer mounted in a microprocessor LSI. The semiconductor integrated circuit is provided with field effect transistors for comparing inputted multibit data signals with stored data and a coincidence-detecting signal line (25) to which current is applied at least while the data signals are compared with stored data. When the data signals coincide with the stored data, the transistors (26) conduct. The number of transistors (26) is equal to that of the inputted data signals. The drains of the transistors (260 are connected in parallel, and the sources are also connected in parallel and supplied with a predetermined voltage. By the integrated circuit, whether or not the inputted data signals coincide with the stored data is detected by detecting the potential of the coincidence-detecting signal line (25) upon a change of the applied current.
    Type: Grant
    Filed: March 9, 2000
    Date of Patent: January 29, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Hisayuki Higuchi, Suguru Tachibana, Koichiro Ishibashi, Keijiro Uehara
  • Patent number: 6121646
    Abstract: A semiconductor integrated circuit, particularly a circuit for a high-speed low-power-consumption table look-aside buffer mounted in a microprocessor LSI. The semiconductor integrated circuit is provided with field effect transistors for comparing inputted multibit data signals with stored data and a coincidence-detecting signal line (25) to which current is applied at least while the data signals are compared with stored data. When the data signals coincide with the stored data, the transistors (26) conduct. The number of transistors (26) is equal to that of the inputted data signals. The drains of the transistors (260 are connected in parallel, and the sources are also connected in parallel and supplied with a predetermined voltage. By the integrated circuit, whether or not the inputted data signals coincide with the stored data is detected by detecting the potential of the coincidence-detecting signal line (25) upon a change of the applied current.
    Type: Grant
    Filed: December 5, 1997
    Date of Patent: September 19, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Hisayuki Higuchi, Suguru Tachibana, Koichiro Ishibashi, Keijiro Uehara
  • Patent number: 5391501
    Abstract: A method for manufacturing a semiconductor integrated circuit device is described. The method comprises forming a plurality of macrocells each comprising a semiconductor integrated circuit on a semiconductor layer of an SOI (silicon on insulator) substrate, subjecting an insulating film for element separation and an insulating film in the substrate to wet etching thereby removing an unnecessary macrocell, and attaching a desired macrocell separated fabricated to the removed macrocell region. The semiconductor integrated circuit device is also described, which is free of defects and has multifunction and high reliability.
    Type: Grant
    Filed: November 5, 1993
    Date of Patent: February 21, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Mitsuo Usami, Keijiro Uehara
  • Patent number: 4675983
    Abstract: An impurity-doped region that serves as an intrinsic base region of a bipolar transistor is formed in a very early stage, and an electrode for taking out the base and a graft base region are formed in a late stage. This makes it possible to reliably connect the intrinsic base region and the graft base region together without permitting them to separate away from each other even when the base region has a very small depth.
    Type: Grant
    Filed: June 5, 1985
    Date of Patent: June 30, 1987
    Assignee: Hitachi, Ltd.
    Inventor: Keijiro Uehara
  • Patent number: 4640721
    Abstract: After an end part of a polycrystalline silicon film has been oxidized from an exposed side surface thereof, a silicon dioxide film formed is removed, and an opening thus provided is used for diffusing an impurity into a semiconductor substrate so as to form a graft base region.This measure is effective for fabricating a semiconductor device of small required area at high precision.
    Type: Grant
    Filed: June 5, 1985
    Date of Patent: February 3, 1987
    Assignee: Hitachi, Ltd.
    Inventors: Keijiro Uehara, Hisayuki Higuchi, Akio Hayasaka
  • Patent number: 4362599
    Abstract: A semiconductor device prepared by forming a silicon substrate of one conductor type having a surface of the (100) crystal plane, opening a rectangular window having sides parallel to the <100> crystal axis, etching the interior of the rectangular window with an anisotropic etching solution to form a dent, removing the oxide film and growing an epitaxial layer of a conductor type opposite to that of the substrate on the entire surface of the substrate, and masking the dent with an oxide film and etching the epitaxial layer with an anisotropic etching solution to flatten the surface of the epitaxial layer, and a method for making this semiconductor device.
    Type: Grant
    Filed: February 23, 1981
    Date of Patent: December 7, 1982
    Assignee: Hitachi, Ltd.
    Inventors: Ichiro Imaizumi, Masatoshi Kimura, Keijiro Uehara
  • Patent number: 4278987
    Abstract: A semiconductor device prepared by forming a silicon substrate of one conductor type having a surface of the (100) crystal plane, opening a rectangular window having sides parallel to the <100> crystal axis, etching the interior of the rectangular window with an anisotropic etching solution to form a dent, removing the oxide film and growing an epitaxial layer of a conductor type opposite to that of the substrate on the entire surface of the substrate, and masking the dent with an oxide film and etching the epitaxial layer with an anisotropic etching solution to flatten the surface of the epitaxial layer, and a method for making this semiconductor device.
    Type: Grant
    Filed: October 12, 1978
    Date of Patent: July 14, 1981
    Assignee: Hitachi, Ltd.
    Inventors: Ichiro Imaizumi, Masatoshi Kimura, Keijiro Uehara
  • Patent number: 3977920
    Abstract: A lateral transistor or the like is made by the steps of forming a first insulating layer on a semiconductor substrate and providing a first hole in this insulating layer so as to expose a first surface portion of the substrate. An impurity of a first conductivity type is introduced through the hole and a second hole is formed in the insulating layer so as to expose a second surface portion of the substrate spaced apart from the first portion. Then, a second insulating layer of a material different from that of the first layer is formed on the first insulating layer and on the first and second surface portions of the substrate. Subsequently, third and fourth holes are formed in the second insulating layer within the confines of these holes to expose at least portions of the first and second surface portions of the substrate. Then, an impurity of a second conductivity type is introduced into the exposed first and second surface portions of the substrate through the third and fourth holes.
    Type: Grant
    Filed: August 23, 1974
    Date of Patent: August 31, 1976
    Assignee: Hitachi, Ltd.
    Inventors: Ichiro Imaizumi, Tadao Kaji, Akio Hayasaka, Keijiro Uehara