Patents by Inventor Keinosuke Toriyama

Keinosuke Toriyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor integrated circuit device
    Patent number: 7016214
    Abstract: A semiconductor integrated circuit device capable of achieving higher integration and simplification of manufacturing processes is provided. Circuitry is provided which includes a first N-channel MOSFET and a first p-channel MOSFET each having a gate insulating dielectric film with a first film thickness, wherein a poly-silicon layer making up a gate electrode is doped with an N-type impurity. The circuitry also includes a second N-channel MOSFET having a gate insulator film with a second film thickness thinner than the first thickness, wherein an N-type impurity is doped into a polysilicon layer making up a gate electrode, and a second P-channel MOSFET with a P-type impurity being doped into a polysilicon layer making up a gate electrode. The gate electrodes of the first N-channel MOSFET and first P-channel MOSFET are integrally formed and mutually connected together.
    Type: Grant
    Filed: October 5, 2004
    Date of Patent: March 21, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Tsuneo Kawamata, Masatoshi Hasegawa, Keinosuke Toriyama, Tomofumi Hokari
  • Semiconductor integrated circuit device
    Publication number: 20050077582
    Abstract: A semiconductor integrated circuit device capable of achieving higher integration and simplification of manufacturing processes is provided. Circuitry is provided which includes a first N-channel MOSFET and a first p-channel MOSFET each having a gate insulating dielectric film with a first film thickness, wherein a poly-silicon layer making up a gate electrode is doped with an N-type impurity. The circuitry also includes a second N-channel MOSFET having a gate insulator film with a second film thickness thinner than the first thickness, wherein an N-type impurity is doped into a polysilicon layer making up a gate electrode, and a second P-channel MOSFET with a P-type impurity being doped into a polysilicon layer making up a gate electrode. The gate electrodes of the first N-channel MOSFET and first P-channel MOSFET are integrally formed and mutually connected together.
    Type: Application
    Filed: October 5, 2004
    Publication date: April 14, 2005
    Inventors: Tsuneo Kawamata, Masatoshi Hasegawa, Keinosuke Toriyama, Tomofumi Hokari