Abstract: A multiprocessor system and method wherein one of the processors is assigned the responsibility of handling interrupts and identifying the next processor to handle an interrupt. When that processor switches tasks and determines that it is no longer the least important processor as far as task priority is concerned, it will then select and transfer its interrupt-related responsibilities (i.e., handling the interrupt and determining the next interrupt-handing processor) to the processor which is executing the least important task. The selected processor will then be designated for handling interrupts unless and until it undergoes a task switch and selects a different processor.

Abstract: A debugger 100 is connected to a multi-processor system configured so that each processor autonomously accesses a shared memory and loads a program stored in the shared memory into storage of the processor. An identifier defined uniquely in the system is included in code of the program module in advance. A GUID detector 118 selects an ID-attached instruction, the identifier being described in a field of the instruction, from the memory image of the local memory of the processor to be inspected and extracts the identifier. A code retriever 120 selects code of a program module, corresponding to the extracted identifier, from a code holder 114. A memory layout output unit 122 outputs the code selected by the code retriever 120, while associating the code with a memory address of the module in the local memory.

Abstract: The present invention relates to a photomultiplier of a fine structure that realizes a high multiplier efficiency. The photomultiplier comprises an outer casing whose interior is maintained at vacuum, and, in the outer case, a photocathode that emits photoelectrons in response to incident light, an electron multiplier section that performs cascade multiplication of the photoelectrons emitted from the photocathode, and an anode for taking out secondary electrons, which are generated at the electron multiplier section, are arranged. In particular, groove portions for performing cascade multiplication of electrons from the photocathode are provided in the electron multiplier section, and on the respective surfaces of each pair of wall portions that define the groove portions are provided with one or more protrusions each having a secondary electron emitting surface formed on the surface thereof.

Abstract: The present invention relates to a photomultiplier having a structure for making it possible to easily realize high detection accuracy and fine processing, and a method of manufacturing the same. The photomultiplier comprises an enclosure having an inside kept in a vacuum state, whereas a photocathode emitting electrons in response to incident light, an electron multiplier section multiplying in a cascading manner the electron emitted from the photocathode, and an anode for taking out a secondary electron generated in the electron multiplier section are arranged in the enclosure. A part of the enclosure is constructed by a glass substrate having a flat part, whereas each of the electron multiplier section and anode is two-dimensionally arranged on the flat part in the glass substrate.

Abstract: Methods and apparatus for cell processors are disclosed. A policy module is loaded from a main memory of a cell processor into the local memory of a selected synergistic processing unit (SPU) under control of an SPU policy module manager (SPMM) running on the SPU. A selected one or more work queues are assigned from a main memory to a selected one or more of the SPUs according to a hierarchy of precedence. A policy module for the selected one or more work queues is loaded to the selected one or more SPUs. The policy module interprets the selected one or more of the selected one or more work queues. Under control of the policy module, work from one or more of the selected one or more work queues is loaded into the local memory of the selected SPU. The work is performed with the selected SPU. After completing the work or upon a pre-emption, control of the selected SPU is returned to the SPMM.

Abstract: Provides a diagnostic apparatus for diagnosing a measured object based on time-series data of a plurality of parameters measured from the measured object. An example of an apparatus includes a change-point score calculating portion for calculating a time-series change-point score with which each of the plurality of parameters changes according to passage of time based on the time-series data on the parameter, a change-point correlation calculating portion for calculating a change-point correlation indicating strength by which each of the plurality of parameters is associated with each of other parameters based on the change-point scores of the parameter and the other parameter, and a parameter outputting portion for outputting a set of parameters of which calculated degrees of associations are higher than a predetermined reference change-point correlation as a set of mutually strongly associated parameters.

Abstract: A first conductive contact connecting a first electrode of an inspection circuit board and one external electrode of a semiconductor integrated circuit is arranged in a fixed member. A second conductive contact connecting a second electrode of a wiring board and the other external electrode of the semiconductor integrated circuit is arranged in a movable member. A third conductive contact connecting one third electrode of the inspection circuit board and the other third electrode of the wiring board is arranged in the movable member. The other third electrode is connected to the second electrode. When the movable member moves to the contacting position, the second conductive contact makes contact with the other external electrode, and the third conductive contact makes contact with the one third electrode.

Abstract: Provides a diagnostic apparatus for diagnosing a measured object based on time-series data of a plurality of parameters measured from the measured object. An example of an apparatus includes a change-point score calculating portion for calculating a time-series change-point score with which each of the plurality of parameters changes according to passage of time based on the time-series data on the parameter, a change-point correlation calculating portion for calculating a change-point correlation indicating strength by which each of the plurality of parameters is associated with each of other parameters based on the change-point scores of the parameter and the other parameter, and a parameter outputting portion for outputting a set of parameters of which calculated degrees of associations are higher than a predetermined reference change-point correlation as a set of mutually strongly associated parameters.

Abstract: A compound represented by the following general formula (1), a salt thereof, or an ester thereof: wherein m represents an integer of 0 to 4, n represents an integer of 5 to 9, and R represents hydrogen atom or a protective group of hydroxyl group, which has reducing actions of blood glucose, plasma insulin, and triglyceride, and is useful for preventive and/or therapeutic treatment of diabetes, complications of diabetes, hyperlipemia and others.

Abstract: A multiprocessor system and method wherein one of the processors is assigned the responsibility of handling interrupts and identifying the next processor to handle an interrupt. When that processor switches tasks and determines that it is no longer the least important processor as far as task priority is concerned, it will then select and transfer its interrupt-related responsibilities (i.e., handling the interrupt and determining the next interrupt-handing processor) to the processor which is executing the least important task. The selected processor will then be designated for handling interrupts unless and until it undergoes a task switch and selects a different processor.

Abstract: Methods and apparatus for migrating and distributing processor tasks on a plurality of multi-processing systems distributed over a network. The multi-processing system includes at least one broadband entity, each broadband entity including a plurality of processing units and synergistic processing units, as well as a shared memory. Tasks from one broadband entity are bundled, migrated and processed remotely on other broadband entities to efficiently use processing resources, and then returned to the migrating broadband entity for completion or continued processing.

Abstract: A system and method is provided for improved interrupt handling via a micro interrupt handler. Upon an interrupt signal being sent to a processor running a task, a first part of the running task is stored to system memory via direct memory access. A micro interrupt handler is read from the system memory to begin handling the interrupt signal. A second part of the running task is stored to system memory via direct memory access. The micro interrupt handler is executed and read and the previous running task is read from direct memory access and restored. Long lag times for interrupt processing and inefficiencies in processor queues are avoided.

Abstract: Direct memory access is provided for each member of a group of IO devices organized into groups. Direct memory access for each IO device is performed in a predetermined order based on the predetermined groups, and may be completed by notification by an interrupt request. A predetermined time delay may be specified between each memory access by each IO device of a predetermined group.

Abstract: A synchronization scheme is provided for a multiprocessor system. In particular, a processor includes a buffer sync controller. The buffer sync controller is operative to allow or deny access by a subprocessor to shared data in a shared memory, such that a processor seeking to write data into or read data from the shared memory must ascertain certain shared parameter data processed by the buffer sync controller.

Abstract: Methods and apparatus provide for associating memory allocation table (MAT) entries with nodes in a binary tree such that the nodes and the entries are grouped into hierarchical levels, each entry including status information; associating the nodes and the entries with segments of a shared memory of a multi-processor system such that higher level nodes and entries are associated with larger numbers of segments of the shared memory and lower level nodes and entries are associated with smaller numbers of segments of the shared memory; initializing the MAT such that the status information of at least a plurality of entries indicates that the associated segment or segments of the shared memory are available for reservation; and selecting one entry in a group of entries in the MAT at a level corresponding to a desired size of the shared memory to be reserved.

Abstract: The present invention is a method for integrating multiple object codes from heterogeneous architectures. For a program on a first processor to reference a program from the name space of a second processor, the object code for the second-processor program is enclosed in a wrapper to create object code in the first-processor name space. The header of the wrapped object code defines a new symbol in the name space of the first processor, and the symbol points to the second-processor object code contained in the wrapped object code. Instead of directly referencing the second-processor object code, the referencing program on the first processor references the wrapped object code. A system tool can be used to wrap the object code which runs on the second processor.

Abstract: The present invention provides methods and apparatus for transferring and storing data among processors and memory in a multiprocessor system. The data is compressed locally before it is sent to a shared memory. The memory stores the data in its compressed state, but the data is aligned in the memory in the same manner as uncompressed data would be. A tag table keeps track of the compression type and compressed data size for a set of data at a given address block. A data compressor and a data expander may be implemented in a direct memory access controller accessible to multiple coprocessors, or the compressor and the expander may be implemented within the coprocessors.