Abstract: In a method for producing a multilayer printed wiring board, first and second copper foils for surface layer are disposed on both sides of an inner wiring substrate so that each of first and second prepreg sheets provided with through-holes is sandwiched between each of the copper foils for surface layer and each face of the substrate, the through-holes being formed therethrough at desired positions corresponding to positions where the connecting pads on each face of the substrate are formed, and the resulting structure is integrally bonded by applying heat and pressure thereto. During the heat- and pressure-processing step, the through-holes within the prepreg sheets are filled with a resin fused from the prepreg sheets. After selectively removing the copper foil for surface layer within an area which matches each of the connecting pads, the resin is selectively removed by the irradiation of laser beams to form via holes and allow the connecting pads to be exposed.

Abstract: A multilayered board is formed by applying a photosensitive insulating resin layer on a laminated plate on which via holes and a circuit pattern are formed, followed by the formation of photoviaholes through the photoprinting method, plating and etching. Then, the multilayered board is adhered to another multilayered board prepared in the same manner through a prepreg layer and a conductive paste while applying heat and pressure to give a multilayer printed wiring board. According to this method, electrical connections between the conductive layer of the upper-most layer and the inner conductive layers, between the inner conductive layers, and between the lower-most conductive layer and the inner conductive layers can be achieved through the photoviaholes and the conductive paste. Therefore, it is not necessary to form through-holes for the electrical connection therebetween. The multilayer printed wiring boards can be substantially improved in the number of layers and wiring density thereof.

Abstract: An engine-driven power generating system having a bridge circuit section in which low-frequency switching elements are driven alternately by low-frequency drive signals, and high-frequency switching elements driven by high-frequency drive signals during the ON period of the low-frequency switching elements are connected in a bridge network, and an inverter circuit section having a drive signal supply circuit for supplying low-frequency and high-frequency drive signals are each supplied to the low-frequency and high-frequency switching elements that form a pair; the a-c voltage generated by an engine-driven a-c generator is converted into d-c voltage that is in turn converted into a predetermined level of low-frequency a-c voltage; characterized in that an overcurrent detecting circuit for detecting an overcurrent flowing in the bridge circuit section at a level higher than a predetermined level, a drive-signal control circuit that outputs to a drive-signal supply circuit, when the overcurrent detecting circui

Abstract: A decode circuit decodes digital signals X1 and X0 as multiplicand to output decoded signals A0-A3. One of these decoded signals A3-A0 is set to be logic 1 in accordance with a value of a multiplicand. A logical operation circuit includes a plurality of operation circuits. Each logical operation circuit performs an independent operation for obtaining a logical value of each bit of the digital signal which is a multiplication result, based on the decoded signals A0-A3 and the digital signals R1 and R0 as a multiplier. Therefore, a result of an operation of a certain bit does not affect results of operations of other bits, so that the logical operation of each bit can be conducted without waiting termination of the logical operations of other bits, which enables high-speed multiplications.

Abstract: Disclosed is a process for preparing a multi-layer printed wiring board including the step of forming a through hole and an external layer circuit on a laminated board of double-sided or multi-layer construction. Then the laminated board is coated over the whole front and back surfaces with a paste-like heat-resistant resin, simultaneously filling the through hole with a resin. A copper foil is disposed on the whole front and back surfaces of the laminated board. Next, the arrangement is heated and pressure-molded in a vacuum. The copper foil is then removed to form an intermediate laminated board. Then, multilayer molding of at least two sets of intermediate laminated boards with a prepreg interposed therebetween is preformed via a step of heat and pressure-molding. In using the penetrated through hole as the divided via hole, there is no longer a restriction of the thickness of the respective divided via holes on the same lattice point.

Abstract: A binary data converter is adapted to convert a positive binary data into a negative binary data represented by a complement on two and vice verse. The conversion is effected as follows. A least significant bit of an inputted binary data is outputted as the least significant bit of the converted binary date as it is. With respect to bit signal other than the least significant bit, respective input bit signals less significant than the corresponding input bit signal are ORed. Depending on the result thereof, inverted or non-inverted signals of the corresponding input bit signals are outputted as the bit signals of the converted binary data. Therefore, carry delay is not generated, and thus the operation speed can be increased. Further, the simple circuit structures can reduce the number of required elements.

Abstract: An updown counter up-counts binary data stored in respective flip-flops in an up-count mode, and down-counts the binary data stored in the respective flip-flops in a down-count mode. When a command for an up-count mode is applied by an up/down control signal, the binary data stored in the respective flip-flops is converted into a complement on two after converting it into a complement on one. When a command for a down-count mode is applied by an up/down control signal, the binary data stored in the respective flip-flops is converted into a complement on one after converting it into a complement on two. The converted data is used to rewrite the data stored in the respective flip-flops.

Abstract: A cathode-ray tube panel, wherein the outer surface (12) of the cathode-ray tube panel (10) is made in the form of a roughened surface (14) having microscopic irregularities and the roughened surface is formed with a thin electrically conductive film (15) made of SnO.sub.2 and Sb.sub.2 O.sub.3, thereby making the panel both antistatic and antireflective.

Abstract: An input analogue signal is converted to a two-valued signal and then it is supplied to each encoder. Each gate signal forming circuit forms a gate signal based on an input digital signal. Each encoder encodes the above stated two-valued signal, an encoding function thereof being determined based on the above stated gate signal. As a result, each encoder outputs a result of multiplication of the two-valued signal and the digital signal in the form of a binary digital signal.

Abstract: A semiconductor integrated circuit which is comprised of the following; a plurality of comparators which respectively compare analog values inputted for multiplication with individual reference voltages respectively, multiplication means which controls values outputted from those plural comparators by applying signals corresponding to digital values inputted for multiplication and outputs the product of the values outputted from those plural comparators and the digital values, and a complement operation circuit which converts the value outputted from multiplication means into complement when the digital value is negative.

Abstract: An A/D converter of a serial-parallel comparison type has both multiplying functions of an analog input data and a digital input data. The analog input data V.sub.X is converted into a digital code I.sub.c corresponding to two more significant digits, by a first parallel comparing portion and a first determining circuit, and converted into a digital code I.sub.f corresponding to two less significant digits by a second parallel comparing portion and a second determining circuit. The digital codes I.sub.c and I.sub.f are alternately applied to a control circuit by a first selector circuit. Two more significant bits R.sub.c and two less significant bits R.sub.f of a 4-bit digital input data are respectively applied to a control signal generating circuit by a second selector circuit. Multiplications of R.sub.c I.sub.c, RfIc, R.sub.c I.sub.f and R.sub.f I.sub.f are serially performed within the time period of one conversion by the control signal generating circuit and the control circuit.

Abstract: A semiconductor integrated circuit so arranged that selection is made out of output signals of a decision circuit which determines the levels of analog values inputted as an object for multiplication and multiplication is carried out with respect to the selected signal and the digital value inputted as an object for multiplication, the result of the multiplication being added with the digital value as shifted to the higher position of specified bits, a multiplication result being thereby calculated with respect to the analog value and the digital value, whereby the required area of wiring connections is reasonably reduced and faster operation is assured.

Abstract: A semiconductor integrated circuit includes a plurality of comparators for comparing an analog input with reference voltage or voltages, holding means for holding a digital value, and control means for controlling the outputs of the plurality of comparators by a control signal responsive to the digital value to output the multiplication result of the output values of the plurality of comparators and the digital value. Thus, the integrated circuit can construct a circuit having functions of an A/D converter and a multiplier on one chip.

Abstract: A wafer testing device in which a plurality of wafers can be tested simultaneously significantly reducing the time required for testing each chip. A prober is provided which receives a wafer to be tested. A probe card is coupled to the prober having a window through which a plurality of semiconductor memory chips on the wafer are observable. A plurality of probes are coupled to the periphery of the window in such a manner that the probes can be brought into contact with bonding pads on the plurality of semiconductor memory chips. A tester is connected to the probes which is capable of simultaneously testing each of the plurality of chips.

Abstract: A capacitive element of a semiconductor integrated circuit comprising a first conductor provided in the input side and a second conductor provided in the output side further includes a third conductor to be connected with the first conductor. The front and back surfaces of the second conductor are entirely covered by the first and third conductors. Portions connecting the first and third conductors are arranged along the peripheral edge portions of the second conductor excepting a signal extracting portion.