Abstract: In a semiconductor device having a plurality of area sections defined therein, a basic multi-layered wiring arrangement is provided on a semiconductor substrate, and both the substrate and the basic multi-layered wiring arrangement have an internal electronic circuit area section and an I/O area section defined in each of the area sections. A plurality of electronic circuits are produced in the circuit area section, and an I/O buffer is produced in the I/O area section. The I/O buffer is suitably and electrically connected to the internal electronic circuits in the basic arrangement. An external multi-layered wiring arrangement is provided on the basic arrangement, and has a power supply electrode pad, a ground electrode pad, at least one signal electrode pad formed and arranged on a top surface thereof, and a wiring-layout produced therein to establish electrical connections between the I/O buffer and the electrode pads.

Abstract: In a semiconductor device having a plurality of area sections defined therein, a basic multi-layered wiring arrangement is provided on a semiconductor substrate, and both the substrate and the basic multi-layered wiring arrangement have an internal electronic circuit area section and an I/O area section defined in each of the area sections. A plurality of electronic circuits are produced in the circuit area section, and an I/O buffer is produced in the I/O area section. The I/O buffer is suitably and electrically connected to the internal electronic circuits in the basic arrangement. An external multi-layered wiring arrangement is provided on the basic arrangement, and has a power supply electrode pad, a ground electrode pad, at least one signal electrode pad formed and arranged on a top surface thereof, and a wiring-layout produced therein to establish electrical connections between the I/O buffer and the electrode pads.

Abstract: A method and apparatus for wire routing of a semiconductor integrated circuit wherein the interconnection between the functional blocks disposed on a chip of the semiconductor integrated circuit having four or more wiring layers is implemented by computers. A plurality of adjacent wiring layers form a single set, and for at least two sets, the wire routing between terminals of the functional blocks lying on the wiring layers formed by the sets is carried out for each set independently from the other set. A plurality of computers are used, which communicate with each other through their network. A file system of one computer is shared between the two computers so that the wire routing process program, input information on the wire routing and a wire routing result can be stored within the shared file system, whereby an efficient concurrent processing is possible and the processing speed can be improved while the number of wiring layers dealt with by each wire routing process are reduced.

Abstract: First random test patterns and a second random test pattern having a "don't care" bit pattern are sequentially supplied to a suspect logic gate as well as to two known good logic gates, the second random test pattern is discriminated when the two known good logic gates produce different output signals due to the "don't care" bit pattern, and a comparator can compare the output signal of the suspect logic gate with the output signal of either known good logic gate only when the first random test patterns are distributed thereto, thereby preventing an analyst from mis-judge on the basis of inconsistency due to the second random test pattern.