Patents by Inventor Keisuke Tokubuchi
Keisuke Tokubuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11551973Abstract: A method for manufacturing a semiconductor device includes providing an adhesive film over a first surface of a semiconductor wafer on which a semiconductor device layer and a bump electrically connected to the semiconductor device layer are formed, forming a slit in the adhesive film, fragmenting the semiconductor wafer into semiconductor chips along the slit, and connecting the bump to a wiring of a circuit board within the adhesive film.Type: GrantFiled: March 1, 2021Date of Patent: January 10, 2023Assignee: KIOXIA CORPORATIONInventors: Takanobu Ono, Keisuke Tokubuchi, Akira Tomono
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Patent number: 11309219Abstract: A method for manufacturing a semiconductor device of an embodiment includes: dividing a semiconductor wafer including a plurality of chip areas each having a columnar electrode and dicing areas, along the dicing areas to form a plurality of semiconductor chips; sticking a first resin film on the plurality of semiconductor chips while filling parts of the first resin film in gaps each present between adjacent ones of the plurality of semiconductor chips; forming trenches narrower in width than the gaps in the first resin film filled in the gaps; and sequentially picking up the plurality of semiconductor chips each having the first resin film, and mounting the picked semiconductor chip on a substrate.Type: GrantFiled: March 5, 2020Date of Patent: April 19, 2022Assignee: Kioxia CorporationInventors: Akira Tomono, Keisuke Tokubuchi, Takanobu Ono
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Publication number: 20220059407Abstract: A method for manufacturing a semiconductor device includes providing an adhesive film over a first surface of a semiconductor wafer on which a semiconductor device layer and a bump electrically connected to the semiconductor device layer are formed, forming a slit in the adhesive film, fragmenting the semiconductor wafer into semiconductor chips along the slit, and connecting the bump to a wiring of a circuit board within the adhesive film.Type: ApplicationFiled: March 1, 2021Publication date: February 24, 2022Inventors: Takanobu ONO, Keisuke TOKUBUCHI, Akira TOMONO
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Publication number: 20210082761Abstract: A method for manufacturing a semiconductor device of an embodiment includes: dividing a semiconductor wafer including a plurality of chip areas each having a columnar electrode and dicing areas, along the dicing areas to form a plurality of semiconductor chips; sticking a first resin film on the plurality of semiconductor chips while filling parts of the first resin film in gaps each present between adjacent ones of the plurality of semiconductor chips; forming trenches narrower in width than the gaps in the first resin film filled in the gaps; and sequentially picking up the plurality of semiconductor chips each having the first resin film, and mounting the picked semiconductor chip on a substrate.Type: ApplicationFiled: March 5, 2020Publication date: March 18, 2021Applicant: Kioxia CorporationInventors: Akira TOMONO, Keisuke Tokubuchi, Takanobu Ono
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Patent number: 10950468Abstract: A semiconductor manufacturing apparatus according to an embodiment irradiates a semiconductor substrate with laser to form modified regions along an intended cut line in the semiconductor substrate. A light source emits the laser. An optical system comprises an objective lens configured to focus the laser in the semiconductor substrate. A light modulator is capable of modulating an energy density distribution of the laser. A controller controls the light modulator to displace a peak position of the energy density distribution of the laser from an optical axis of the objective lens in a relative movement direction of the optical system with respect to the semiconductor substrate.Type: GrantFiled: March 5, 2018Date of Patent: March 16, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Makoto Minaminaka, Tsutomu Fujita, Keisuke Tokubuchi, Akira Tomono, Takanobu Ono
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Publication number: 20190080940Abstract: A semiconductor manufacturing apparatus according to an embodiment irradiates a semiconductor substrate with laser to form modified regions along an intended cut line in the semiconductor substrate. A light source emits the laser. An optical system comprises an objective lens configured to focus the laser in the semiconductor substrate. A light modulator is capable of modulating an energy density distribution of the laser. A controller controls the light modulator to displace a peak position of the energy density distribution of the laser from an optical axis of the objective lens in a relative movement direction of the optical system with respect to the semiconductor substrate.Type: ApplicationFiled: March 5, 2018Publication date: March 14, 2019Applicant: TOSHIBA MEMORY CORPORATIONInventors: Makoto MINAMINAKA, Tsutomu FUJITA, Keisuke TOKUBUCHI, Akira TOMONO, Takanobu ONO
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Patent number: 6739326Abstract: By preventing warping of chips when detaching individual chips from a dicing sheet, improvement in quality without cracks and in productivity is realized. A collet (115) used in a step of detaching chips (110) discretely divided as bonded to a dicing sheet (109) from the dicing sheet has a flat attraction surface made of a porous material of a size equal to or larger than the chip size. Alternatively, the collet may have a chip attraction groove containing poles, balls or hemispheres, for example, to prevent warping of chips. In the step of detaching each chip from the dicing sheet, a means for reducing the bonding force of the dicing sheet, such as heating device or cooling device, may be provided. Thus, warping or cracking can be prevented in a process of thinned semiconductor substrate. Additionally, since the means for reducing the bonding force of the dicing sheet is provided in a semiconductor manufacturing equipment, breakage or cracking of chips can be prevented more reliably.Type: GrantFiled: November 13, 2001Date of Patent: May 25, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Tetsuya Kurosawa, Hideo Numata, Keisuke Tokubuchi
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Publication number: 20020026931Abstract: By preventing warping of chips when detaching individual chips from a dicing sheet, improvement in quality without cracks and in productivity is realized. A collet (115) used in a step of detaching chips (110) discretely divided as bonded to a dicing sheet (109) from the dicing sheet has a flat attraction surface made of a porous material of a size equal to or larger than the chip size. Alternatively, the collet may have a chip attraction groove containing poles, balls or hemispheres, for example, to prevent warping of chips. In the step of detaching each chip from the dicing sheet, a means for reducing the bonding force of the dicing sheet, such as heating device or cooling device, may be provided. Thus, warping or cracking can be prevented in a process of thinned semiconductor substrate. Additionally, since the means for reducing the bonding force of the dicing sheet is provided in a semiconductor manufacturing equipment, breakage or cracking of chips can be prevented more reliably.Type: ApplicationFiled: November 13, 2001Publication date: March 7, 2002Applicant: Kabushiki Kaisha Toshiba.Inventors: Tetsuya Kurosawa, Hideo Numata, Keisuke Tokubuchi
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Patent number: 6352073Abstract: By preventing warping of chips when detaching individual chips from a dicing sheet, improvement in quality without cracks and in productivity is realized. A collet (115) used in a step of detaching chips (110) discretely divided as bonded to a dicing sheet (109) from the dicing sheet has a flat attraction surface made of a porous material of a size equal to or larger than the chip size. Alternatively, the collet may have a chip attraction groove containing poles, balls or hemispheres, for example, to prevent warping of chips. In the step of detaching each chip from the dicing sheet, a means for reducing the bonding force of the dicing sheet, such as heating device or cooling device, may be provided. Thus, warping or cracking can be prevented in a process of thinned semiconductor substrate. Additionally, since the means for reducing the bonding force of the dicing sheet is provided in a semiconductor manufacturing equipment, breakage or cracking of chips can be prevented more reliably.Type: GrantFiled: September 24, 1999Date of Patent: March 5, 2002Assignee: Kabushiki Kaisha ToshibaInventors: Tetsuya Kurosawa, Hideo Numata, Keisuke Tokubuchi
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Patent number: 6337258Abstract: Grooves are formed in an element formation surface of a wafer along dicing lines or chip dividing lines. The grooves are deeper than a thickness of a finished chip. A holding member is attached on the element formation surface of the wafer. A bottom surface of the wafer is lapped and polished to the thickness of the finished chip, thereby dividing the wafer into chips. The chips are transferred while being held by porous adsorption.Type: GrantFiled: July 20, 2000Date of Patent: January 8, 2002Assignee: Kabushiki Kaisha ToshibaInventors: Hideo Nakayoshi, Shinya Takyu, Keisuke Tokubuchi, Tetsuya Kurosawa
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Patent number: 6294439Abstract: Grooves are formed in a surface of a wafer, on which semiconductor elements are formed, along dicing lines or chip parting lines on the wafer. The grooves are deeper than the thickness of a finished chip, and each of them has a curved bottom surface. A holding sheet is attached on the surface of the wafer on which the semiconductor elements are formed. Subsequently, the rear surface of the wafer is lapped and polished to the thickness of the finished chip, thereby dividing the wafer into chips. Even after the wafer is divided into the chips, the lapping and polishing is continued until the thickness of the wafer becomes equal to the thickness of the finished chip. The lapping and polishing amount required to attain the thickness of the finished chip after the lapped face of the wafer reaches the bottom surface of the groove, and a depth of a region of the curved bottom surface of the groove define a ratio of not less than 0.3.Type: GrantFiled: February 7, 2000Date of Patent: September 25, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Shigeo Sasaki, Shinya Takyu, Keisuke Tokubuchi, Koichi Yazima, Hideo Nakayoshi
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Patent number: 6238515Abstract: A wafer transfer apparatus for sticking a wafer, which is divided into a multiplicity of chips and which has its surface stuck with a protective tape, to a ring frame by a transfer tape, includes: a positioning unit capable of disposing the protective tape stuck wafer on a positioning table and capable of performing a position adjustment of the wafer in longitudinal, lateral and rotational directions, so that the wafer is located in a reference position; a transfer tape mount unit capable of disposing the protective tape stuck wafer, which has been located in the reference position by the positioning unit, on a transfer tape mount table, and capable of sticking a transfer tape to both a ring frame disposed round periphery of the wafer and back of the wafer, so that the wafer and the ring frame are stuck to each other and integrated; and a protective tape peeling unit capable of disposing the wafer, which has its back covered with the transfer tape and which has been integrated with the ring frame by the transType: GrantFiled: August 18, 1999Date of Patent: May 29, 2001Assignees: Lintec Corporation, Kabushiki Kaisha ToshibaInventors: Masaki Tsujimoto, Kenji Kobayashi, Hideo Numata, Keisuke Tokubuchi
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Patent number: 6184109Abstract: Grooves are formed in a surface of a wafer, on which surface semiconductor elements are formed, along dicing lines on the wafer by means of a dicing blade. The grooves are deeper than a thickness of a finished chip. Alternatively, grooves are formed in a surface of a wafer, on which surface semiconductor elements are formed, along chip parting lines on the wafer by etching. Like the grooves described above, the grooves are deeper than a thickness of a finished chip. A holding member is attached on the surface of the wafer on which the semiconductor elements are formed. The bottom surface of the wafer is lapped and polished to the thickness of the finished chip, thereby dividing the wafer into chips. When the wafer is divided into the chips, the lapping and polishing is continued until the thickness of the wafer becomes equal to the thickness of the finished chip, even after the wafer has been divided into the chips by the lapping and polishing.Type: GrantFiled: January 21, 1999Date of Patent: February 6, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Shigeo Sasaki, Shinya Takyu, Keisuke Tokubuchi, Koichi Yazima, Hideo Nakayoshi
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Patent number: 5888883Abstract: Grooves are formed in a surface of a wafer, on which surface semiconductor elements are formed, along dicing lines. The grooves are deeper than a thickness of a finished chip. A holding member is attached on the surface of the wafer on which the semiconductor elements are formed. A bottom surface of the wafer is lapped and polished to the thickness of the finished chip, thereby dividing the wafer into chips. When the wafer is divided into the chips, the lapping and polishing is continued until the thickness of the wafer becomes equal to the thickness of the finished chip, even after the wafer has been divided into the chips by the lapping and polishing.Type: GrantFiled: April 24, 1998Date of Patent: March 30, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Shigeo Sasaki, Shinya Takyu, Keisuke Tokubuchi, Koichi Yazima