Abstract: A display panel comprises a plurality of scan lines and a scan driving circuit having a plurality of stages in series, each of stages comprising a shift register unit and a compensation unit. The shift register unit and the compensation unit in the same stage are at the opposite sides of the display panel. Each of the scan lines is electrically connected with the shift register unit and the compensation unit in the same stage. When a first shift register unit of a first stage located on a side of the display panel outputs a scan signal to a terminal of the scan line, one of a second shift register unit of a previous stage and a third shift register unit of a next stage both located on the other side controls the compensation unit outputting a control signal to the other terminal of the scan line synchronously.

Abstract: A display device where a memory circuit is installed into each pixel without generating flicker, including a plurality of pixels arranged in a matrix, wherein each pixel has a light-transmissive element controlling the amount of transmissive light in response to a voltage difference between a first electrode and a second electrode, a memory circuit storing the voltage level of the first electrode, and a controller. In the case where the first electrode has a positive voltage level with respect to the second electrode at a refreshing timing, the controller makes the memory circuit store the voltage level of the first electrode, applies a first predetermined voltage to the second electrode to increase the voltage level of the first electrode by the first predetermined voltage, and discharges the first electrode so that the first electrode has a negative voltage level with respect to the second electrode.

Abstract: The display device according to the present invention comprises a substrate and at least one optical coupler having an optical receiver and an optical transmitter formed on the substrate, wherein the optical transmitter transmits an optical signal to the optical receiver.

Abstract: A drive circuit is disclosed. The drive circuit includes a first p-typed thin film transistor (PTFT), a second PTFT, a first n-typed thin film transistor (NTFT), a second NTFT and a capacitor. The drain of the first PTFT is coupled to a first electrical line, and the gate thereof is coupled to a first clock line. The drain of the second PTFT is coupled to a second clock line, and the source thereof is coupled to an output. The source of the first NTFT is coupled to a second electrical line, and the gate thereof is couple to an output of a preceding drive circuit. The source of the second NTFT is couple to a third electrical line, the gate thereof is coupled to a third clock line, and the drain thereof is coupled to the output. The capacitor has one end coupled to the second electrical line, while the other end is coupled to the source of the first PTFT, the drain of the first NTFT and the gate of the second PTFT.

Abstract: A shift register is provided. In each of successively cascaded shift register units, for a first switch, control and output terminals are coupled to a first node and an output node respectively, and an input terminal receives a first clock signal. For a second switch, input and output terminals are coupled to the control terminal of the second switch and the first node respectively. For a third switch, a control terminal is coupled to the first node, and an input terminal receives the first clock signal. A first capacitor is coupled between an output terminal of the third switch and the first node. For a fourth switch, an input terminal is coupled to the first node, and an output terminal is coupled to a low voltage terminal. For a current shift register, a control terminal of the second switch receives an output signal generated by previous shift register unit.

Abstract: A shift register is provided. In the shift register, each of successively cascaded shift register units includes first and second switches and first and second capacitors. For the first switch, a control terminal is coupled to a first node, an input terminal receives a first clock signal, and an output terminal is coupled to an output node. The first capacitor is coupled between the first node and the output node. The second capacitor is coupled between the output node and a ground terminal. For the second switch, an input terminal receives a second clock signal, and an output terminal is coupled to the first node. A carry signal is generated at the first node. For the N-th shift register unit, a control terminal of the second switch receives the carry signal generated at the first node of the previous shift register unit.

Abstract: An operating method and a display panel are provided. The method Includes a number steps. A display panel is provided, and has a pixel element, the pixel element including an n-bit memory, n being a positive integer in accordance with image data. The pixel element is driven by using a k-th data voltage, k being smaller than 2n, the k-th data voltage ranging between a plurality of data voltages having absolute values in an increasing order. When k is odd, the k-th data voltage has one of positive and negative polarities. When k is even, the k-th data voltage has the other one of positive and negative polarities.

Abstract: A display device includes a plurality of pixels arranged in a matrix with columns and rows. A source driver provides either analogue or digital image data for the pixels. Each pixel includes a plurality of sub-pixels. Each sub-pixel includes a display components, a memory unit for memorizing gradation display data included in the digital image data provided by the source driver for the display component, and a data switching unit for switching data providing for the display component to either the gradation display data memorized in the memory unit or the analogue image data provided by the source driver.

Abstract: A display device includes a display unit and a plurality of refreshing units. The display unit has a plurality of the display areas. Each of the display areas has a plurality of pixels. Each of the pixels has a memory. The refreshing units respectively control to refresh the pixels of the corresponding display areas at different time periods. Thus, the produced peak current during the pixel refreshing can be reduced, and the stored pixel data can be maintained.

Abstract: A display apparatus includes a plurality of pixels. Each pixel has a light emitting unit, a memory cell, and a driving circuit. The memory cell stores an image data. The driving circuit is electrically connected with the light emitting unit and the memory cell, and drives the light emitting unit according to the image data.

Abstract: This present invention provides a liquid crystal display (LCD) device in which the sub-pixel is provided with three different voltage levels, so that image quality is improved without the configuration of additional gate lines. The present invention overcomes the reduction of aperture ratio in conventional LCD devices due to the configuration of additional gate lines. By the present invention, the white washout problem relating to the off-axis viewing angle can be overcome while the aperture ratio is not reduced.

Abstract: An operating method and a display panel are provided. The method Includes a number steps. A display panel is provided, and has a pixel element, the pixel element including an n-bit memory, n being a positive integer in accordance with image data. The pixel element is driven by using a k-th data voltage, k being smaller than 2n, the k-th data voltage ranging between a plurality of data voltages having absolute values in an increasing order. When k is odd, the k-th data voltage has one of positive and negative polarities. When k is even, the k-th data voltage has the other one of positive and negative polarities.

Abstract: A display panel is provided, including an image data storage capacitor, a capacitive element, and four switches. The image data storage capacitor stores an image data. The sample unit has a control terminal for receiving a sample control signal. The capacitive element has a first terminal coupled to a pixel electrode of the image data storage capacitor via the sample unit. The first refresh unit has a control terminal coupled to the first terminal. The second refresh unit has a control terminal for receiving a refresh control signal. The third and first refresh unites are serially coupled with each other between a corresponding source line and the image data storage capacitor for receiving a data signal. The shunt unit has a control terminal coupled to the pixel electrode, a data terminal coupled to the first terminal, and another data terminal for receiving a shunt control signal.

Abstract: A switch circuit, a pixel element and a display panel are provided. The switch circuit is for the pixel element, and includes switches. A switch is turned on to perform a sample operation on the pixel element. Another switch has a control terminal coupled to an image data storage capacitor of the pixel element via the switch, a data terminal to a corresponding source line, and another data terminal to the image data storage capacitor. During the sample operation, the second switch stores an image data of the image data storage capacitor in a parasitic gate capacitor existing on its control terminal. The parasitic gate capacitor maintains its stored data from the sample operation to a refresh operation in which the pixel element is refreshed. The second switch selectively electrically connects its two data terminals with each other according to stored image data in the parasitic gate capacitor.

Abstract: A pixel element, a display panel, and a control method thereof are provided. The method includes a number of steps. An image data is stored in an image data storage capacitor of the display panel. A sample operation is performed to store the image data in a capacitive element. Based on the stored image data in the capacitive element, a refresh operation is performed to refresh the image data stored in the image data storage capacitor. The refreshed image data has the same polarity as the polarity of the image data stored in the image data storage capacitor in the sample operation.

Abstract: This present invention provides a liquid crystal display (LCD) device in which the sub-pixel is provided with three different voltage levels, so that image quality is improved without the configuration of additional gate lines. The present invention overcomes the reduction of aperture ratio in conventional LCD devices due to the configuration of additional gate lines. By the present invention, the white washout problem relating to the off-axis viewing angle can be overcome while the aperture ratio is not reduced.

Abstract: A display device where a memory circuit is installed into each pixel without generating flicker, including a plurality of pixels arranged in a matrix, wherein each pixel has a light-transmissive element controlling the amount of transmissive light in response to a voltage difference between a first electrode and a second electrode, a memory circuit storing the voltage level of the first electrode, and a controller. In the case where the first electrode has a positive voltage level with respect to the second electrode at a refreshing timing, the controller makes the memory circuit store the voltage level of the first electrode, applies a first predetermined voltage to the second electrode to increase the voltage level of the first electrode by the first predetermined voltage, and discharges the first electrode so that the first electrode has a negative voltage level with respect to the second electrode.

Abstract: The invention provides a liquid crystal display device capable of ensuring high transparent aperture ratio and realizing high resolution. The liquid crystal display device comprises: a first transparent substrate (301); a second transparent substrate (301) facing the first transparent substrate; an insulating layer (304) formed on the second transparent substrate; a plurality of pixel electrodes (20) formed on the insulating layer in a matrix form; an opposite electrode (24) formed on the first transparent substrate, facing the pixel electrode, and having a predetermined potential; a liquid crystal layer (303) existing between the pixel electrode and the opposite electrode; a pixel circuit (305) formed on the upper surface of the second transparent substrate, applying a voltage on the pixel electrode; and at least one parallel electrode (307?) parallel with the pixel electrode in the insulating layer.

Abstract: A display apparatus includes a plurality of pixels. Each pixel has a light emitting unit, a memory cell, and a driving circuit. The memory cell stores an image data. The driving circuit is electrically connected with the light emitting unit and the memory cell, and drives the light emitting unit according to the image data.

Abstract: A display device includes a display unit and a plurality of refreshing units. The display unit has a plurality of the display areas. Each of the display areas has a plurality of pixels. Each of the pixels has a memory. The refreshing units respectively control to refresh the pixels of the corresponding display areas at different time periods. Thus, the produced peak current during the pixel refreshing can be reduced, and the stored pixel data can be maintained.