Patents by Inventor Keitarou Kondou

Keitarou Kondou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100104478
    Abstract: The present invention is to present a sample analyzer comprising: a reagent container holder for holding a reagent container for containing a reagent to be used for analyzing a sample; a measurement unit for measuring a value representing an amount of the reagent in the reagent container held by the reagent container holder; an instruction receiver for receiving an instruction to obtain a remaining amount of the reagent in the reagent container; a measurement controller for controlling the measurement unit so as to measure the value representing the amount of the reagent in the reagent container, when the instruction receiver has received the instruction; and a remaining reagent amount obtainer for obtaining remaining reagent amount information indicating the remaining amount of the reagent in the reagent container, based on a measurement result by the measurement unit.
    Type: Application
    Filed: October 26, 2009
    Publication date: April 29, 2010
    Applicant: SYSMEX CORPORATION
    Inventor: Keitarou KONDOU
  • Publication number: 20100031124
    Abstract: A transmission apparatus includes: a CRC encoding processing unit configured to include a plurality of generating polynomials for an CRC encoding processing with each of a plurality of data of which the code lengths differ as a target, and employ the optimal generating polynomial out of the plurality of generating polynomials to perform the CRC encoding processing; and a transmission unit configured to transmit data obtained by the CRC encoding processing unit performing the CRC encoding processing.
    Type: Application
    Filed: December 18, 2008
    Publication date: February 4, 2010
    Applicant: Sony Corporation
    Inventors: Masashi Shinagawa, Makoto Noda, Hiroyuki Yamagishi, Keitarou Kondou
  • Publication number: 20090300462
    Abstract: Disclosed herein is an encoding apparatus which combines an RLL code word and an error correction code word, with an interleaving technique when encoding, including: an error correction encoding section; an interleaving section; and an RLL encoding section, wherein, if an address i (i is an integer satisfying relations 0?i<k×m) is assigned to each symbol of k×m error correction code words and xij is denoting the number of symbols included in n symbols of a jth (j is an integer satisfying relations 0?j<m) code word of m error correction code words to serve as symbols corresponding to the address i of an information word of an RLL code, for any j, the interleaving section interleaves a series inside an information word of the RLL code word so that the following relations are satisfied: ? i ? x ij = n ? ? and ? ? x ij > 0.
    Type: Application
    Filed: May 22, 2009
    Publication date: December 3, 2009
    Inventors: Keitarou Kondou, Makoto Noda
  • Patent number: 7603608
    Abstract: Systems and methods for ending, storing and transmitting data generate error correcting code words for data that is provided for each of a plurality of channels. The error correcting code words include data from each of the plurality of channels and the resultant data is rearranged into a plurality of data blocks such that a loss of the rearranged physically adjacent data block reduces an amount of data lost from a common error correcting code word.
    Type: Grant
    Filed: November 2, 2005
    Date of Patent: October 13, 2009
    Assignee: Sony Corporation
    Inventors: Keitarou Kondou, Makoto Noda
  • Publication number: 20090224032
    Abstract: A sample analyzer for analyzing a measurement sample prepared by mixing a specimen and a reagent includes a movement unit for moving at least one of a specimen container, a reagent container and an accommodation unit for accommodating the specimen container or the reagent container with identification information; an identification data acquirer for reading at least one of identification information provided to the specimen container, the reagent container or the accommodation unit; and a controller for controlling operations of the movement unit and the identification data acquirer such that the movement unit moves each identification information so that the identification data acquirer sequentially reads; the controller judges each identification information is normally read; the movement unit moves each identification information to be read again; and the identification data acquirer reads identification information at a read position is disclosed.
    Type: Application
    Filed: February 17, 2009
    Publication date: September 10, 2009
    Applicant: SYSMEX CORPORATION
    Inventors: Keitarou KONDOU, Hiroyuki MATSUURA
  • Publication number: 20090221090
    Abstract: A sample analysis apparatus for analyzing a measurement sample prepared by mixing a sample and a reagent includes a condition memory for storing information regarding a plurality of read conditions; an ID acquirer for reading out identification information at a predetermined position in accordance with a predetermined read condition, the identification information being assigned for identification of at least one of a sample container, a reagent container, and a holding section for holding the sample container or the reagent container; an ID acquisition checker for determining whether or not the ID acquirer has successfully read out the identification information; and a read condition changer for changing the predetermined read condition to a different read condition different from the predetermined read condition stored in the condition memory when the ID acquisition checker has determined that the readout operation was not successful.
    Type: Application
    Filed: January 13, 2009
    Publication date: September 3, 2009
    Applicant: SYSMEX CORPORATION
    Inventors: Keitarou KONDOU, Hiroyuki Matsuura
  • Publication number: 20080320370
    Abstract: Disclosed herein is a CRC generator polynomial select method for selecting a generator polynomial to be used in CRC coding processing and/or CRC processing of inspecting a CRC processing result, the CRC generator polynomial select method may include a first process of finding largest minimum Hamming distances Max.dmin; a second process of finding code lengths n for each of the largest minimum Hamming distances Max.dmin and determining a range expressed by relations nmin (r, Max.dmin)?n?nmax (r, Max.dmin); a third process of searching all generator polynomials G(x) for specific generator polynomials G(x); and a fourth process of selecting final generator polynomials G(x) each having a smallest term count w and a lowest code undetected-error probability Pud from the specific generator polynomials G(x).
    Type: Application
    Filed: June 22, 2007
    Publication date: December 25, 2008
    Applicant: Sony Corporation
    Inventors: Masashi Shinagawa, Keitarou Kondou, Makoto Noda
  • Publication number: 20080056401
    Abstract: Disclosed herein is a decoding apparatus for decoding channel input bits from a partial-response channel output in accordance with a trellis obtained by combining a coding constraint and state transitions of a partial response for a case in which the length of a memory required for describing the coding constraint is greater than the length of a channel memory of the partial response. The apparatus may include a first calculation unit configured to carry out a first calculation on first branch information, which may be defined as information on first branches included in three or more branches merging in a state determined in advance, and first path information defined as information on first paths for the first branches; and a second calculation unit configured to carry out a second calculation on a first calculation value obtained as a result of the first calculation.
    Type: Application
    Filed: July 20, 2007
    Publication date: March 6, 2008
    Applicant: Sony Corporation
    Inventors: Hiroyuki Yamagishi, Keitarou Kondou
  • Patent number: 7222287
    Abstract: The present invention realizes a decoder and an error position polynomial calculation method which realize erasure corrections by making less changes to a conventional Berlekamp algorithm calculation circuit. An error position polynomial ?(x) is calculated on the basis of a syndrome S0, S1, . . . , S2t?1 and erasure position data Er0, Er1, . . . , Er2t?1 as Galois field expressions of erasure positions. In addition, switching of connection between buffers holding uncompleted operation results and an operator is controlled based on the number of erased received symbols and the number of processing steps, so that derivations of both the erasure position polynomial and the error position polynomial from erasure position data can be realized by the same circuit (an error position polynomial calculator).
    Type: Grant
    Filed: February 26, 2004
    Date of Patent: May 22, 2007
    Assignee: Sony Corporation
    Inventor: Keitarou Kondou
  • Patent number: 7188299
    Abstract: In order to reproduce data in a stable manner by correction of random and burst errors of a wide range without lowering a transfer speed, C2 error correction for correcting an inter-sector error is carried out in addition to the conventional C1 error correction for correcting an error generated in a sector. The configuration of an error correction unit (or an ECC block) including C1 and C2 codes is formed as a track. That is to say, one track is used as the base of an ECC block unit. In this way, two ECC block units never exist in the same track.
    Type: Grant
    Filed: July 22, 2003
    Date of Patent: March 6, 2007
    Assignee: Sony Corporation
    Inventors: Toshiyuki Nakagawa, Keitarou Kondou, Hiroaki Eto, Yoshihide Shimpuku
  • Publication number: 20060107173
    Abstract: The present invention provides a data processing method that can reduce the number of data blocks belonging to a same error-correcting code word for two-dimensional error bursts that give rise to errors over a plurality of transmission channels.
    Type: Application
    Filed: November 2, 2005
    Publication date: May 18, 2006
    Inventors: Keitarou Kondou, Makoto Noda
  • Publication number: 20050166123
    Abstract: A transmission/reception system is provided. In a transmitter, error correction data is added to each set of N TS packets, an RTP packet is generated by collecting M (N>M) TS packets with the added error correction data and sequentially assigning a sequence number to each set of the M TS packets, and each RTP packet is transmitted by converting the RTP packets into data transmittable to a receiver. In the receiver, the data from the transmitter is received, the RTP packet is acquired from the data received, it is judged, from the sequence number of the RTP packet, whether there is any dropped packet not received, and the dropped packet is corrected by using the RTP packets, if there is a dropped packet not received.
    Type: Application
    Filed: December 22, 2004
    Publication date: July 28, 2005
    Applicant: SONY CORPORATION
    Inventors: Kaoru Yanamoto, Makoto Noda, Keitarou Kondou, Masashi Shinagawa, Takatsuna Sasaki
  • Publication number: 20050005193
    Abstract: In order to reproduce data in a stable manner by correction of random and burst errors of a wide range without lowering a transfer speed, C2 error correction for correcting an inter-sector error is carried out in addition to the conventional C1 error correction for correcting an error generated in a sector. The configuration of an error correction unit (or an ECC block) including C1 and C2 codes is formed as a track. That is to say, one track is used as the base of an ECC block unit. In this way, two ECC block units never exist in the same track.
    Type: Application
    Filed: July 22, 2003
    Publication date: January 6, 2005
    Inventors: Toshiyuki Nakagawa, Keitarou Kondou, Hiroaki Eto, Yoshihide Shimpuku
  • Publication number: 20040255226
    Abstract: The present invention realizes a decoder and an error position polynomial calculation method which realize erasure corrections by making less changes to a conventional Berlekamp algorithm calculation circuit. An error position polynomial &sgr;(x) is calculated on the basis of a syndrome S0, S1, . . . , S2t−1 and erasure position data Er0, Er1, . . . , Er2t−1 as Galois field expressions of erasure positions. In addition, switching of connection between buffers holding uncompleted operation results and an operator is controlled based on the number of erased received words and the number of processing steps, so that derivations of both the erasure position polynomial and the error position polynomial from erasure position data can be realized by the same circuit (an error position polynomial calculator).
    Type: Application
    Filed: February 26, 2004
    Publication date: December 16, 2004
    Inventor: Keitarou Kondou