Abstract: A servomechanism for controlling the position of a magnetic-tape playback head (16) with respect to a track (24) of digital data on a magnetic tape (22) positions the head by reference to an error signal that error-signal-generation circuitry (FIG. 10). generates. Sample-clock signals obtained from simultaneously read azimuth-recorded data tracks clock respective frequency dividers (52 and 54), and a phase detector 56 generates the error signal by comparing the frequency dividers' outputs.

Abstract: An automatic scan tracking, helical tape type of data recorder is disclosed herein along with its method of operation. Data is written onto magnetic recording tape along with data retrieval information by means of a rotating scanner assembly forming part of the recorder as the recording tape moves at a given recording speed in cooperative engagement with the scanner assembly. Data is normally retrieved from the recording tape along with the data retrieval information by means of the rotating scanner assembly as the recording tape moves longitudinally at the same given recording speed. In operation, the rotating scanner assembly of the recorder retrieves data and data retrieval information from a segment of the recording tape while the latter is not moving, that is, during a period when the tape is stationary for enabling adjustment of the read head position relative to the track depending on the evaluation of the data resulting from the stationary tape read.

Abstract: A helical tape recording and reproducing system which has longitudinal physical address track for recording physical address data relating to the physical layout of the tape and a logical address track that contains data relating to the content of the recorded helical tracks. Each address track has recorded segments with each of said segments containing data corresponding to a particular pair of helical tracks recorded in said helical recording area. Each segment has a multiple bit front field of a first predetermined timing synchronization bit pattern, a first predefined synchronizing word, a multiple bit segment information field of data, a second predefined synchronizing word and a multiple bit rear field of a second predetermined timing synchronization bit pattern.