Patents by Inventor Keith Bargroff
Keith Bargroff has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11955932Abstract: Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.Type: GrantFiled: May 23, 2023Date of Patent: April 9, 2024Assignee: pSemi CorporationInventors: Jonathan James Klaren, David Kovac, Eric S. Shapiro, Christopher C. Murphy, Robert Mark Englekirk, Keith Bargroff, Tero Tapio Ranta
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Patent number: 11948897Abstract: Integrated circuits (ICs) that avoid or mitigate creation of changes in accumulated charge in a silicon-on-insulator (SOI) substrate, particularly an SOI substrate having a trap rich layer. In one embodiment, a FET is configured such that, in a standby mode, the FET is turned OFF while maintaining essentially the same VDS as during an active mode. In another embodiment, a FET is configured such that, in a standby mode, current flow through the FET is interrupted while maintaining essentially the same VGS as during the active mode. In another embodiment, a FET is configured such that, in a standby mode, the FET is switched into a very low current state (a “trickle current” state) that keeps both VGS and VDS close to their respective active mode operational voltages. Optionally, S-contacts may be formed in an IC substrate to create protected areas that encompass FETs that are sensitive to accumulated charge effects.Type: GrantFiled: February 11, 2022Date of Patent: April 2, 2024Assignee: pSemi CorporationInventors: Robert Mark Englekirk, Keith Bargroff, Christopher C. Murphy, Tero Tapio Ranta, Simon Edward Willard
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Publication number: 20240094757Abstract: A controllable temperature coefficient bias (CTCB) circuit is disclosed. The CTCB circuit can provide a bias to an amplifier. The CTCB circuit includes a variable with temperature (VWT) circuit having a reference circuit and a control circuit. The control circuit has a control output, a first current control element and a second current control element. Each current control element has a “controllable” resistance. One of the two current control elements may have a relatively high temperature coefficient and another a relatively low temperature coefficient. A controllable resistance of one of the current control elements increases when the controllable resistance of the other current control element decreases. However, the “total resistance” of the current control circuit remains constant with a constant temperature. The VWT circuit has an output with a temperature coefficient that is determined by the relative amount of current that flows through each current control element of the control circuit.Type: ApplicationFiled: July 26, 2023Publication date: March 21, 2024Inventors: Robert Mark Englekirk, Keith Bargroff, Christopher C. Murphy, Tero Tapio Ranta
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Patent number: 11929824Abstract: An outdoor satellite receiving unit (ODU) receives several independent satellite signals, selects two signals with a switch matrix, downconverts the two signals to a bandstacked signal with a high and a low band signal, and outputs the bandstacked signal on the same cable to receiver units. Several satellite signals can be selected in groups of two or more and output to independent receiver units. Signal selecting is performed at the received radio frequency (RF) and bandstacking is performed with a single downconversion step to an intermediate frequency (IF). Channel stacking on the same cable of more than two channels from several satellites can be achieved by using frequency agile downconverters and bandpass filters prior to combining at the IF output. A slow transitioning switch minimizes signal disturbances when switching and maintains input impedance at a constant value.Type: GrantFiled: February 22, 2023Date of Patent: March 12, 2024Assignee: Entropic Communications, LLCInventors: Branislav Petrovic, Dale Hancock, Jeremy Goldblatt, Keith Bargroff
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Publication number: 20240039479Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit and stacked transistors standby current during operation in the standby mode and to reduce impedance presented to the gates of the stacked transistors during operation in the active mode while maintaining voltage compliance of the stacked transistors during both modes of operation.Type: ApplicationFiled: August 9, 2023Publication date: February 1, 2024Inventors: Poojan Wagh, Kashish Pal, Robert Mark Englekirk, Tero Tapio Ranta, Keith Bargroff, Simon Edward Willard
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Patent number: 11867584Abstract: Methods and devices to mitigate time varying impairments in sensors are described. The application of such methods and devices to pressure sensors facing time varying parasitic capacitances due to water droplets is detailed. Benefits of auto-zeroing technique as adopted in disclosed devices is also described.Type: GrantFiled: September 5, 2021Date of Patent: January 9, 2024Assignee: pSemi CorporationInventors: Vishnu Srinivasan, Ion Opris, Keith Bargroff
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Publication number: 20230387864Abstract: Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.Type: ApplicationFiled: May 23, 2023Publication date: November 30, 2023Inventors: Jonathan James Klaren, David Kovac, Eric S. Shapiro, Christopher C. Murphy, Robert Mark Englekirk, Keith Bargroff, Tero Tapio Ranta
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Patent number: 11742802Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit and stacked transistors standby current during operation in the standby mode and to reduce impedance presented to the gates of the stacked transistors during operation in the active mode while maintaining voltage compliance of the stacked transistors during both modes of operation.Type: GrantFiled: November 19, 2021Date of Patent: August 29, 2023Assignee: pSemi CorporationInventors: Poojan Wagh, Kashish Pal, Robert Mark Englekirk, Tero Tapio Ranta, Keith Bargroff, Simon Edward Willard
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Publication number: 20230254058Abstract: An outdoor satellite receiving unit (ODU) receives several independent satellite signals, selects two signals with a switch matrix, downconverts the two signals to a bandstacked signal with a high and a low band signal, and outputs the bandstacked signal on the same cable to receiver units. Several satellite signals can be selected in groups of two or more and output to independent receiver units. Signal selecting is performed at the received radio frequency (RF) and bandstacking is performed with a single downconversion step to an intermediate frequency (IF). Channel stacking on the same cable of more than two channels from several satellites can be achieved by using frequency agile downconverters and bandpass filters prior to combining at the IF output. A slow transitioning switch minimizes signal disturbances when switching and maintains input impedance at a constant value.Type: ApplicationFiled: February 22, 2023Publication date: August 10, 2023Inventors: Branislav Petrovic, Dale Hancock, Jeremy Goldblatt, Keith Bargroff
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Patent number: 11720136Abstract: A controllable temperature coefficient bias (CTCB) circuit is disclosed. The CTCB circuit can provide a bias to an amplifier. The CTCB circuit includes a variable with temperature (VWT) circuit having a reference circuit and a control circuit. The control circuit has a control output, a first current control element and a second current control element. Each current control element has a “controllable” resistance. One of the two current control elements may have a relatively high temperature coefficient and another a relatively low temperature coefficient. A controllable resistance of one of the current control elements increases when the controllable resistance of the other current control element decreases. However, the “total resistance” of the current control circuit remains constant with a constant temperature. The VWT circuit has an output with a temperature coefficient that is determined by the relative amount of current that flows through each current control element of the control circuit.Type: GrantFiled: November 15, 2022Date of Patent: August 8, 2023Assignee: pSemi CorporationInventors: Robert Mark Englekirk, Keith Bargroff, Christopher C. Murphy, Tero Tapio Ranta
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Patent number: 11664769Abstract: Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.Type: GrantFiled: June 17, 2022Date of Patent: May 30, 2023Assignee: pSemi CorporationInventors: Jonathan James Klaren, David Kovac, Eric S. Shapiro, Christopher C. Murphy, Robert Mark Englekirk, Keith Bargroff, Tero Tapio Ranta
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Publication number: 20230152836Abstract: A controllable temperature coefficient bias (CTCB) circuit is disclosed. The CTCB circuit can provide a bias to an amplifier. The CTCB circuit includes a variable with temperature (VWT) circuit having a reference circuit and a control circuit. The control circuit has a control output, a first current control element and a second current control element. Each current control element has a “controllable” resistance. One of the two current control elements may have a relatively high temperature coefficient and another a relatively low temperature coefficient. A controllable resistance of one of the current control elements increases when the controllable resistance of the other current control element decreases. However, the “total resistance” of the current control circuit remains constant with a constant temperature. The VWT circuit has an output with a temperature coefficient that is determined by the relative amount of current that flows through each current control element of the control circuit.Type: ApplicationFiled: November 15, 2022Publication date: May 18, 2023Inventors: Robert Mark Englekirk, Keith Bargroff, Christopher C. Murphy, Tero Tapio Ranta
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Patent number: 11616585Abstract: An outdoor satellite receiving unit (ODU) receives several independent satellite signals, selects two signals with a switch matrix, downconverts the two signals to a bandstacked signal with a high and a low band signal, and outputs the bandstacked signal on the same cable to receiver units. Several satellite signals can be selected in groups of two or more and output to independent receiver units. Signal selecting is performed at the received radio frequency (RF) and bandstacking is performed with a single downconversion step to an intermediate frequency (IF). Channel stacking on the same cable of more than two channels from several satellites can be achieved by using frequency agile downconverters and bandpass filters prior to combining at the IF output. A slow transitioning switch minimizes signal disturbances when switching and maintains input impedance at a constant value.Type: GrantFiled: September 13, 2021Date of Patent: March 28, 2023Assignee: Entropic Communications, LLCInventors: Branislav Petrovic, Dale Hancock, Jeremy Goldblatt, Keith Bargroff
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Publication number: 20230084770Abstract: Temperature compensation circuits and methods for adjusting one or more circuit parameters of a power amplifier (PA) to maintain approximately constant Gain versus time during pulsed operation sufficient to substantially offset self-heating of the PA. Some embodiments compensate for PA Gain “droop” due to self-heating using a Sample and Hold (S&H) circuit. The S&H circuit samples and holds an initial temperature of the PA at commencement of a pulse. Thereafter, the S&H circuit generates a continuous measurement that corresponds to the temperature of the PA during the remainder of the pulse. A Gain Control signal is generated that is a function of the difference between the initial temperature and the operating temperature of the PA as the PA self-heats for the duration of the pulse. The Gain Control signal is applied to one or more adjustable or tunable circuits within a PA to offset the Gain droop of the PA.Type: ApplicationFiled: September 15, 2022Publication date: March 16, 2023Inventors: Tero Tapio Ranta, Keith Bargroff, Christopher C. Murphy, Robert Mark Englekirk
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Patent number: 11507125Abstract: A controllable temperature coefficient bias (CTCB) circuit is disclosed. The CTCB circuit can provide a bias to an amplifier. The CTCB circuit includes a variable with temperature (VWT) circuit having a reference circuit and a control circuit. The control circuit has a control output, a first current control element and a second current control element. Each current control element has a “controllable” resistance. One of the two current control elements may have a relatively high temperature coefficient and another a relatively low temperature coefficient. A controllable resistance of one of the current control elements increases when the controllable resistance of the other current control element decreases. However, the “total resistance” of the current control circuit remains constant with a constant temperature. The VWT circuit has an output with a temperature coefficient that is determined by the relative amount of current that flows through each current control element of the control circuit.Type: GrantFiled: August 10, 2020Date of Patent: November 22, 2022Assignee: pSemi CorporationInventors: Robert Mark Englekirk, Keith Bargroff, Christopher C. Murphy, Tero Tapio Ranta
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Publication number: 20220368287Abstract: Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.Type: ApplicationFiled: June 17, 2022Publication date: November 17, 2022Inventors: Jonathan James Klaren, David Kovac, Eric S. Shapiro, Christopher C. Murphy, Robert Mark Englekirk, Keith Bargroff, Tero Tapio Ranta
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Patent number: 11451205Abstract: Temperature compensation circuits and methods for adjusting one or more circuit parameters of a power amplifier (PA) to maintain approximately constant Gain versus time during pulsed operation sufficient to substantially offset self-heating of the PA. Some embodiments compensate for PA Gain “droop” due to self-heating using a Sample and Hold (S&H) circuit. The S&H circuit samples and holds an initial temperature of the PA at commencement of a pulse. Thereafter, the S&H circuit generates a continuous measurement that corresponds to the temperature of the PA during the remainder of the pulse. A Gain Control signal is generated that is a function of the difference between the initial temperature and the operating temperature of the PA as the PA self-heats for the duration of the pulse. The Gain Control signal is applied to one or more adjustable or tunable circuits within a PA to offset the Gain droop of the PA.Type: GrantFiled: December 16, 2020Date of Patent: September 20, 2022Assignee: pSemi CorporationInventors: Tero Tapio Ranta, Keith Bargroff, Christopher C. Murphy, Robert Mark Englekirk
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Patent number: 11431427Abstract: An outdoor satellite receiving unit (ODU) receives several independent satellite signals, selects two signals with a switch matrix, downconverts the two signals to a bandstacked signal with a high and a low band signal, and outputs the bandstacked signal on the same cable to receiver units. Several satellite signals can be selected in groups of two or more and output to independent receiver units. Signal selecting is performed at the received radio frequency (RF) and bandstacking is performed with a single downconversion step to an intermediate frequency (IF). Channel stacking on the same cable of more than two channels from several satellites can be achieved by using frequency agile downconverters and bandpass filters prior to combining at the IF output. A slow transitioning switch minimizes signal disturbances when switching and maintains input impedance at a constant value.Type: GrantFiled: May 26, 2020Date of Patent: August 30, 2022Assignee: Entropic Communications, LLCInventors: Branislav Petrovic, Dale Hancock, Jeremy Goldblatt, Keith Bargroff
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Publication number: 20220246550Abstract: Integrated circuits (ICs) that avoid or mitigate creation of changes in accumulated charge in a silicon-on-insulator (SOI) substrate, particularly an SOI substrate having a trap rich layer. In one embodiment, a FET is configured such that, in a standby mode, the FET is turned OFF while maintaining essentially the same VDS as during an active mode. In another embodiment, a FET is configured such that, in a standby mode, current flow through the FET is interrupted while maintaining essentially the same VGS as during the active mode. In another embodiment, a FET is configured such that, in a standby mode, the FET is switched into a very low current state (a “trickle current” state) that keeps both VGS and VDS close to their respective active mode operational voltages. Optionally, S-contacts may be formed in an IC substrate to create protected areas that encompass FETs that are sensitive to accumulated charge effects.Type: ApplicationFiled: February 11, 2022Publication date: August 4, 2022Inventors: Robert Mark Englekirk, Keith Bargroff, Christopher C. Murphy, Tero Tapio Ranta, Simon Edward Willard
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Patent number: 11374540Abstract: Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.Type: GrantFiled: July 22, 2020Date of Patent: June 28, 2022Assignee: pSemi CorporationInventors: Jonathan James Klaren, David Kovac, Eric S. Shapiro, Christopher C. Murphy, Robert Mark Englekirk, Keith Bargroff, Tero Tapio Ranta