Abstract: Layers suitable for stacking in three dimensional, multi-layer modules are formed by interconnecting a ball grid array electronic package to an interposer layer which routes electronic signals to an access plane. The layers are under-filled and may be bonded together to form a stack of layers. The leads on the access plane are interconnected among layers to form a high-density electronic package.

Abstract: Layers suitable for stacking in three dimensional, multi-layer modules are formed by interconnecting a ball grid array electronic package to an interposer layer which routes electronic signals to an access plane. The layers are under-filled and may be bonded together to form a stack of layers. The leads on the access plane are interconnected among layers to form a high-density electronic package.

Abstract: Prepackaged chips, such a memory chips, are vertically stacked and bonded together with their terminals aligned. The exterior lead frames are removed including that portion which extends into the packaging. The bonding wires are now exposed on the collective lateral surface of the stack. In those areas where no bonding wire was connected to the lead frame, a bare insulative surface is left. A contact layer is disposed on top of the stack and vertical metalizations defined on the stack to connect the ends of the wires to the contact layer and hence to contact pads on the top surface of the contact layer. The vertical metalizations are arranged and configured to connect all commonly shared terminals of the chips, while the control and data input/output signals of each chip are separately connected to metalizations, which are disposed in part on the bare insulative surface.

Abstract: Layers suitable for stacking in three dimensional, multi-layer modules are formed by interconnecting a ball grid array electronic package to an interposer layer which routes electronic signals to an access plane. The layers are under-filled and may be bonded together to form a stack of layers. The leads on the access plane are interconnected among layers to form a high-density electronic package.

Abstract: Prepackaged chips, such a memory chips, are vertically stacked and bonded together with their terminals aligned. The exterior lead frames are removed including that portion which extends into the packaging. The bonding wires are now exposed on the collective lateral surface of the stack. In those areas where no bonding wire was connected to the lead frame, a bare insulative surface is left. A contact layer is disposed on top of the stack and vertical metalizations defined on the stack to connect the ends of the wires to the contact layer and hence to contact pads on the top surface of the contact layer. The vertical metalizations are arranged and configured to connect all commonly shared terminals of the chips, while the control and data input/output signals of each chip are separately connected to metalizations, which are disposed in part on the bare insulative surface.

Abstract: Prepackaged chips, such a memory chips, are vertically stacked and bonded together with their terminals aligned. The exterior lead frames are removed including that portion which extends into the packaging. The bonding wires are now exposed on the collective lateral surface of the stack. In those areas where no bonding wire was connected to the lead frame, a bare insulative surface is left. A contact layer is disposed on top of the stack and vertical metalizations defined on the stack to connect the ends of the wires to the contact layer and hence to contact pads on the top surface of the contact layer. The vertical metalizations are arranged and configured to connect all commonly shared terminals of the chips, while the control and data input/output signals of each chip are separately connected to metalizations, which are disposed in part on the bare insulative surface.

Abstract: Layers suitable for stacking in three dimensional, multi-layer modules are formed by interconnecting a ball grid array electronic package to an interposer layer which routes electronic signals to an access plane. The layers are under-filled and may be bonded together to form a stack of layers. The leads on the access plane are interconnected among layers to form a high-density electronic package.

Abstract: Layers suitable for stacking in three dimensional, multi-layer modules are formed by interconnecting a ball grid array electronic package to an interposer layer which routes electronic signals to an access plane. The layers are under-filled and may be bonded together to form a stack of layers. The leads on the access plane are interconnected among layers to form a high-density electronic package.

Abstract: A field programmable gate array, an access lead network coupled to the FPGA, and a plurality of memories electrically coupled to the access lead network. The FPGA, access lead network, and plurality of memories are arranged and configured to operate with a variable word width, namely with a word width between 1 and a maximum number of bits. The absolute maximum word width may be as large as m.times.N where m is the number of word width bits per memory chip and N is the number of memory chips.

Abstract: A method of making a stacked assembly of integrated circuits (ICs) from prepackaged semiconductor chips is disclosed. The method involves the steps of first starting with a commercially available prepackaged semiconductor chip (e.g. a thin small outline package (TSOP)), that contains bare silicon die within an encapsulant and removing at least part of the encapsulant from the lateral sides to expose the wire bonds. More such prepackaged chips are modified and stacked upon one another. Metalization is performed on the stack to interconnect the layers. An additional embodiment discloses the use of lead frames to the stack of integrated circuits. Additional disclosure covers a method of stacking printed circuit boards (PCBs). A compact and low cost mini-computer is also disclosed that is made using methods of the present invention.

Abstract: A method for interconnecting stacked layers containing integrated circuit die and a device built from the method is disclosed. The stacked layers are bonded together to form a module whereby individual I/O pads of the integrated circuit die are rerouted to at least one edge of the module. The rerouted leads terminate at the edge. Channels are formed in a surface of the module or on the surface of a layer whereby the rerouted leads are disposed within the channel. The entire surface of the edge or layer is metalized and a predetermined portion of the metalization removed such that the rerouted leads within each channel are electrically connected to each other.

Abstract: A field programmable gate array, an access lead network coupled to the FPGA, and a plurality of memories electrically coupled to the access lead network. The FPGA, access lead network, and plurality of memories are arranged and configured to operate with a variable word width, namely with a word width between 1 and a maximum number of bits. The absolute maximum word width may be as large as m.times.N where m is the number of word width bits per memory chip and N is the number of memory chips.

Abstract: Prepackaged chips, such a memory chips, are vertically stacked and bonded together with their terminals aligned. The exterior lead frames are removed including that portion which extends into the packaging. The bonding wires are now exposed on the collective lateral surface of the stack. In those areas where no bonding wire was connected to the lead frame, a bare insulative surface is left. A contact layer is disposed on top of the stack and vertical metalizations defined on the stack to connect the ends of the wires to the contact layer and hence to contact pads on the top surface of the contact layer. The vertical metalizations are arranged and configured to connect all commonly shared terminals of the chips, while the control and data input/output signals of each chip are separately connected to metalizations, which are disposed in part on the bare insulative surface.