Abstract: A method of providing ad hoc verification for a simulation includes generating a cumulative record of a state value for the simulation of a circuit design, comparing the cumulative record of the state value to a golden record of the state value to obtain a comparison result, and performing ad hoc verification of the circuit design using the comparison result.

Abstract: A method of providing accelerated post-silicon testing for a silicon hardware includes computing a simulation cumulative record of state using a plurality of test instructions and a cycle breakpoint, performing a simulation of an instrumented logic design using the plurality of test instructions and the cycle breakpoint, manufacturing the silicon hardware using the instrumented logic design, computing a silicon cumulative record of state by executing the plurality of instructions using the silicon hardware; and comparing the simulation cumulative record of state to the silicon cumulative record of state.

Abstract: A method of providing accelerated post-silicon testing for a silicon hardware includes computing a simulation cumulative record of state using a plurality of test instructions and a cycle breakpoint, performing a simulation of an instrumented logic design using the plurality of test instructions and the cycle breakpoint, manufacturing the silicon hardware using the instrumented logic design, computing a silicon cumulative record of state by executing the plurality of instructions using the silicon hardware; and comparing the simulation cumulative record of state to the silicon cumulative record of state.

Abstract: A method of providing ad hoc verification for a simulation includes generating a cumulative record of a state value for the simulation of a circuit design, comparing the cumulative record of the state value to a golden record of the state value to obtain a comparison result, and performing ad hoc verification of the circuit design using the comparison result.

Abstract: The present invention is a system and method for "checking the use of synchronization locks in a multi-threaded computer program" (hereinafter "WARLOCK II"). In Warlock II a set of source code representing a process which includes multiple threads may be annotated by the developer using a "NOTE" macro to describe the desired operation of the locks. This annotated source code is passed to a modified ANSI C compiler which outputs a special file designated a ".ll" file, as for example, file "foo.ll". This special ".ll" file is then processed as input along with other designated ".ll" files which might be related, by a "wlanalyze" program which will check the source code of the target programs in the ".ll" files to determine whether their use of synchronization locks is consistent with the intended use as specified in the annotations.