Abstract: An economical method of detecting and suppressing ringing artifacts during digital image resizing is presented. The economical method substitutes costly division calculations with cost effective comparator operations. The method also includes improved image sharpening when up-sampling an image.

Abstract: A method and apparatus for operating a content addressable memory (CAM) and a ternary CAM (TCAM) are described including an encoding circuit for encoding an incoming CAM or TCAM word to produce an encoded CAM or TCAM word such that a one-bit mismatch between a comparand and the incoming CAM or TCAM word results in at least a M-bit mismatch between said encoded CAM or TCAM word and a similarly encoded comparand, a circuit for precharging a match line to a predetermined state before a comparison between the encoded CAM or TCAM word and said similarly encoded comparand and a memory storage location for storing the encoded CAM or TCAM word.

Abstract: The invention provides techniques for secure messages transmission using a public key system to exchange secret keys. A first entity creates public and private keys by generating a product n of two large, randomly chosen prime numbers, and then generating random matrices {A, C}, in the group GL(r,Zn) with a chosen matrix rank r such that AC is not equal to CA, and then generating a matrix B=CAC, and finding a matrix G that commutes with C. Matrices A, B, G and the integers n and r are then published as the public key and matrix C is then kept as the private key. A second entity then obtains the public key and calculates a secret matrix D that commutes with G, and further calculates the matrices K=DBD and E=DAD. The message to be sent is then encrypted using matrix K as the secret key and then sent to the first entity with matrix E. First entity then retrieves secret matrix K using K=CEC and then decrypts the received encrypted message using the retrieved secret matrix K.

Abstract: A calibration system for calibrating a linearity corrector using the sum of filter products is proved, along with a method of calibrating the linearity corrector. The calibration system includes a first and second signal generator for introducing test signals into a signal processing system, such as an ADC. An acquisition memory and processor are provided for acquiring and analyzing the output of the signal processing system and then programming the filter coefficients into the linearity corrector. The method of calibration analyzes acquired intermodulation and harmonic components from the signal processing system and then finds the amplitude and phase response for the filters. The amplitude and phase response is then used to determine a set of filter coefficients.

Abstract: A method and system for calculating resample output values from input samples and their associated sample values. A resampling circuit calculates a frequency value for a sine-wave model from a sample set of the input samples and determines whether the frequency value is in a frequency range. In the case where the frequency value is in the frequency range, a sinusoidal transition model is determined based on the sample set. However, if the frequency value is outside of the frequency range, a non-sinusoidal model is determined based on the sample set. The resampling circuit then calculates resample output values from the resulting sinusoidal or non-sinusoidal model.

Abstract: Systems and methods are provided for caching dynamic arrays. According to one aspect, a cache memory device is provided for caching dynamic arrays or dynamic overlays. According to one embodiment, the device includes a plurality of memory cells and at least one register for storing access information to access at least one array stored in the plurality of memory cells. According to another aspect, an electronic system is provided that includes a main memory, a dynamic array cache memory device, a general cache memory device, and a processor. The dynamic array cache memory device is coupled to the main memory and adapted for caching array data. The general cache memory device is coupled to the main memory and is adapted for caching regular data. The processor is coupled to and adapted for communication with the main memory, the general cache memory device, and the dynamic array cache memory device.

Abstract: Systems and methods are provided for caching dynamic arrays. According to one aspect, a cache memory device is provided for caching dynamic arrays or dynamic overlays. According to one embodiment, the device includes a plurality of memory cells and at least one register for storing access information to access at least one array stored in the plurality of memory cells. According to another aspect, an electronic system is provided that includes a main memory, a dynamic array cache memory device, a general cache memory device, and a processor. The dynamic array cache memory device is coupled to the main memory and adapted for caching array data. The general cache memory device is coupled to the main memory and is adapted for caching regular data. The processor is coupled to and adapted for communication with the main memory, the general cache memory device, and the dynamic array cache memory device.

Abstract: Systems and methods are provided for writing code to access data arrays. One aspect provides a method of accessing a memory array. Data is provided within a one-dimensional array of allocated memory. A dimensional dynamic overlay is declared from within a block of statements, and the declaration initializes various attributes within an array attribute storage object. The data is accessed from within the block of statements as a dimensional indexed array using the array attribute storage object. Another aspect provides a method of creating and accessing a dimensional dynamic array. A dimensional dynamic array is declared from within a block of statements, and memory storage for the array is dynamically allocated. A dynamic overlay storage object is also provided and its attributes are initialized from the dynamic array declaration. The data is accessed as a dimensional indexed array from within the block of statements using the array attribute storage object.

Abstract: A method and system for calculating resample output values from input samples and their associated sample values. A resampling circuit calculates a frequency value for a sine-wave model from a sample set of the input samples and determines whether the frequency value is in a frequency range. In the case where the frequency value is in the frequency range, a sinusoidal transition model is determined based on the sample set. However, if the frequency value is outside of the frequency range, a non-sinusoidal model is determined based on the sample set. The resampling circuit then calculates resample output values from the resulting sinusoidal or non-sinusoidal model.

Abstract: An economical method of detecting and suppressing ringing artifacts during digital image resizing is presented. The economical method substitutes costly division calculations with cost effective comparator operations. The method also includes improved image sharpening when up-sampling an image.

Abstract: A resampling circuit and method where input sample values for samples arranged along a row of a source image are received by a row resampling circuit. The row resampling circuit calculates row output values which are provided to a column resampling circuit that calculates output sample values therefrom. The column resampling circuit includes a shift register that receives the row output values and shifts the row output values through the shift register as the row output samples are calculated. The shift register has a plurality of evenly spaced sample output terminals from which the row output values are sampled by an interpolation circuit for calculation of the output sample values.

Abstract: A dither system for a quantizing device, such as a multi-stage pipelined analog-to-digital converter (ADC), derives a dither signal from a clock signal having a sample frequency, the dither signal having a frequency that is one-third of the sample frequency. The dither signal is easily converted to analog and added at the input of the quantizing device to an analog signal to be digitized. A cancellation signal circuit generates a cosine-wave signal from a digital version of the dither signal and programmable coefficients that are a function of amplitude and phase. The cosine-wave signal is combined with the digital output signal from the quantizing device to produce a corrected digital output signal having reduced quantization distortion.

Abstract: A method and system for determining a transition model between input pixel samples from which output sample values are calculated based on various relative background and brightness conditions of the input pixel samples. A brightness condition is determined from the input sample values associated with the input pixel samples. A first transition model that preserves a constant luminance is used where the brightness condition is indicative of light isolated pixels and a second transition model that preserves a constant darkness is used where the brightness condition is indicative of dark isolated pixels. The resampling circuit may also use alternative models for other brightness conditions, such as for pixel transitions without any emphasis or alternating pixels. The resampling circuit may also perform modified operations for pixels arranged in a diagonal fashion.

Abstract: A linearity compensation circuit provides cancellation of harmonic distortion introduced by a non-linear system into an input signal by providing a separate harmonic correction component for each harmonic of a fundamental frequency of the input signal. The harmonic correction components are summed with a delayed version of the input signal to produce a corrected input signal for input to the non-linear system. The separate harmonic correction components are generated by respective harmonic correction units, each having a programmable input filter, a Hilbert Transformer filter and a plurality of phase shifters. The output of each programmable input filter is input to the Hilbert Transformer filter and a compensating delay.

Abstract: A resampling system and method for producing a resampled destination image from a source image by solving coefficients for a cubic polynomial transition model between first and second adjacent source pixels from the sample values of the first and second samples and approximations of the first and second sample gradients at the first and second samples, respectively. Approximations of the first and second color gradients are based on a multiple of first and second color slopes, such as twice the value of the color slope. The first color slope is calculated from the sample values of a previous pixel and the first sample and the second sample slope is calculated from the sample values of a subsequent sample and the second sample. The resulting gradient approximations and sample values are used in the cubic transition model to calculate an output sample value for rendering a resampled destination image.

Abstract: A resampling circuit and method where input sample values for samples arranged along a row of a source image are received by a row resampling circuit. The row resampling circuit calculates row output values which are provided to a column resampling circuit that calculates output sample values therefrom. The column resampling circuit includes a shift register that receives the row output values and shifts the row output values through the shift register as the row output samples are calculated. The shift register has a plurality of evenly spaced sample output terminals from which the row output values are sampled by an interpolation circuit for calculation of the output sample values.

Abstract: A method and system for determining a transition model between input pixel samples from which output sample values are calculated based on various relative background and brightness conditions of the input pixel samples. A brightness condition is determined from the input sample values associated with the input pixel samples. A first transition model that preserves a constant luminance is used where the brightness condition is indicative of light isolated pixels and a second transition model that preserves a constant darkness is used where the brightness condition is indicative of dark isolated pixels. The resampling circuit may also use alternative models for other brightness conditions, such as for pixel transitions without any emphasis or alternating pixels. The resampling circuit may also perform modified operations for pixels arranged in a diagonal fashion.

Abstract: Asymmetric finite impulse response (FIR) filters are used to estimate gradients for re-sampling models used in image resizing. Better than conventional 3-tap symmetric FIR filters, these filters provide good edge and extended-frequency responses with good narrow peak sharpening characteristics. These filters emphasize accurate edge handling, where gradients are steepest, over accurate peak handling, where gradients are shallowest. This results in superior zone-plate test signals and better resized image quality.

Abstract: Systems and methods are provided for caching dynamic arrays. According to one aspect, a cache memory device is provided for caching dynamic arrays or dynamic overlays. According to one embodiment, the device includes a plurality of memory cells and at least one register for storing access information to access at least one array stored in the plurality of memory cells. According to another aspect, an electronic system is provided that includes a main memory, a dynamic array cache memory device, a general cache memory device, and a processor. The dynamic array cache memory device is coupled to the main memory and adapted for caching array data. The general cache memory device is coupled to the main memory and is adapted for caching regular data. The processor is coupled to and adapted for communication with the main memory, the general cache memory device, and the dynamic array cache memory device.

Abstract: A resampling circuit and method where input sample values for samples arranged along a row of a source image are received by a row resampling circuit. The row resampling circuit calculates row output values which are provided to a column resampling circuit that calculates output sample values therefrom. The column resampling circuit includes a shift register that receives the row output values and shifts the row output values through the shift register as the row output samples are calculated. The shift register has a plurality of evenly spaced sample output terminals from which the row output values are sampled by an interpolation circuit for calculation of the output sample values.