Abstract: Disclosed is a method and apparatus for utilizing a variable gain algorithm for adjusting a capacitor in an automatic radio frequency (RF) impedance matching network. The apparatus may operate in a closed-loop feedback control system, with one or more error signals driving the capacitors within the system. To achieve a critically damped control system response, multiple operating regions for the matching network and its constituent elements may be identified and a set of gains (e.g., different per region) may be applied to the error signals in the control system when operating in those regions. An operating region may be defined by characteristics of the input signals measured by the apparatus, calculated by the apparatus, or the state of the apparatus itself. These features may be arranged in a look up table (or determined by calculation) for the apparatus to use to determine the variable gains in the system.

Abstract: A method for repetitive tuning of a matching network in a radio frequency plasma processing device, the method including detecting a condition within the matching network and determining if the condition is a known condition for the matching network. Also, finding a prior solution and to the condition when the condition is the known condition for the matching network; and replicating the prior solution for the condition in the matching network.

Abstract: A plasma generation system includes an impedance matching network calibrated to map desired matching network impedance values to closest available settings of impedance control components. The tuning controller defines a set of target impedance values spaced-apart throughout the tuning range and drives the matching network to generate a set of closest frame tuning values proximate to each target impedance value. The tuning controller computes interpolated tuning values between adjacent pairs of frame tuning values and stores a tuning database that maps available matching network impedance values to specific sets of settings for the impedance control components. After the calibration stage, the tuning controller automatically utilizes the tuning database to map desired matching network impedance values to available settings of the impedance control components on an ongoing basis. Representative embodiments include variable loading and tuning capacitors in series with a fixed or variable phase-shift inductor.

Abstract: Disclosed is a method and apparatus for utilizing a variable gain algorithm for adjusting a capacitor in an automatic radio frequency (RF) impedance matching network. The apparatus may operate in a closed-loop feedback control system, with one or more error signals driving the capacitors within the system. To achieve a critically damped control system response, multiple operating regions for the matching network and its constituent elements may be identified and a set of gains (e.g., different per region) may be applied to the error signals in the control system when operating in those regions. An operating region may be defined by characteristics of the input signals measured by the apparatus, calculated by the apparatus, or the state of the apparatus itself. These features may be arranged in a look up table (or determined by calculation) for the apparatus to use to determine the variable gains in the system.

Abstract: The present disclosure may include a method for calibrating a capacitor in a matching network in a radio frequency plasma processing device, the method including. The method may include identifying the capacitor in the matching network, measuring the impedance of the matching network as a whole, and driving the capacitor from a zero step value to a predefined step value. The method may further include measuring impedance at each step between the zero step value and the predefined step value, identifying the measured impedance for each step value to a predefined impedance curve, and matching a capacitor position to a specific impedance based on the identifying the measured impedance for each step value to the predefined impedance curve. Calibration of matching networks may also be enhanced by optimizing the steps to percentage reported ratio in the range of capacitor values most frequently used.

Abstract: The present disclosure may include a method for calibrating a capacitor in a matching network in a radio frequency plasma processing device, the method including. The method may include identifying the capacitor in the matching network, measuring the impedance of the matching network as a whole, and driving the capacitor from a zero step value to a predefined step value. The method may further include measuring impedance at each step between the zero step value and the predefined step value, identifying the measured impedance for each step value to a predefined impedance curve, and matching a capacitor position to a specific impedance based on the identifying the measured impedance for each step value to the predefined impedance curve. Calibration of matching networks may also be enhanced by optimizing the steps to percentage reported ratio in the range of capacitor values most frequently used.

Abstract: A method for repetitive tuning of a matching network in a radio frequency plasma processing device, the method including detecting a condition within the matching network and determining if the condition is a known condition for the matching network. Also, finding a prior solution and to the condition when the condition is the known condition for the matching network; and replicating the prior solution for the condition in the matching network.

Abstract: A method for repetitive tuning of a matching network in a radio frequency plasma processing device, the method including detecting a condition within the matching network and determining if the condition is a known condition for the matching network. Also, finding a prior solution and to the condition when the condition is the known condition for the matching network; and replicating the prior solution for the condition in the matching network.

Abstract: A method for repetitive tuning of a matching network in a radio frequency plasma processing device, the method including detecting a condition within the matching network and determining if the condition is a known condition for the matching network. Also, finding a prior solution and to the condition when the condition is the known condition for the matching network; and replicating the prior solution for the condition in the matching network.

Abstract: An apparatus architecture is provided which permits an easily programmed apparatus (10) to serve as an equivalent of an integrated circuit chip, and/or as a building block for a large system. The apparatus (10) is connected to a communications bus (40) which receives apparatus parameter, topological, and microinstruction information from a host processor and/or memory (EPROM). The apparatus includes numerous functional blocks (20), a core (30), and a parametric/microinstruction bus (35). The functional blocks include serial (62,66) and parallel ports (68), D/A (54) and A/D (52) converters, and programmable signal processors (300) which serve to process signal data and are connected in any desired manner through a switching matrix (160) located in the core. The topology of the switching matrix (160) is received via the communications bus (40).

Abstract: A programmable integrated signal processor ("SPROC") is provided having a multiported central memory unit (RAM), a program memory, at least one, and preferably a plurality of digital processors coupled to the multiported RAM and to the program memory, a data flow manager which controls external data flowing into the SPROC and processed data flowing out of the SPROC by acting as an interface of such data with the multiported RAM, input and output ports coupled to the DFM and acting as serial interfaces for the SPROC, and a host port permitting the programming of the SPROC and acting as a parallel interface to the SPROC. SPROCs may be coupled via the input and output ports to provide a system. The SPROC architecture permits the SPROC system to be computationally expandable, to have low latency and parasitic overhead for real time I/O, to efficiently execute a multiple of asynchronous processes, and to easily interface with microprocessors of various formats.

Abstract: Architectures and methods are provided for efficiently dividing a processing task into tasks for a programmable real time signal processor (SPROC) and tasks for a decision-making microprocessor. The SPROC is provided with a non-interrupt structure where data flow is through a multiported central memory. The SPROC is also programmed in an environment which requires nothing more than graphic entry of a block diagram of the user's design. In automatically implementing the block diagram into silicon, the SPROC programming/development environment accounts for and provides software connection and interfaces with a host microprocessor.

Abstract: An event signalling system is provided for a digital signal processor apparatus which has a central data RAM, at least one computing processor, each computing processor having event occurrence circuitry, a plurality of data I/O processors, and a data RAM bus coupled to the data RAM, the computing processor(s) and the I/O processors. The event signalling system includes an address code generating circuit in each data I/O processor for generating different predetermined address codes for each I/O processor and for writing the predetermined address codes onto the data RAM bus upon the occurrence of events of interest. The occurrence of the predetermined address codes on the data RAM bus. are monitored by an address decoder which generates different signals depending upon the predetermined address code found. The signals from the address decoder are carried by a flag bus to the event occurrence circuitry of the computing processor(s), and to the output sections of the I/O processors.

Abstract: Architectures and methods are provided for efficiently dividing a processing task into tasks for a programmable real time signal processor (SPROC) and tasks for a decision-making microprocessor. The SPROC is provided with a non-interrupt structure where data flow is through a multiported central memory. The SPROC is also programmed in an environment which requires nothing more than graphic entry of a block diagram of the user's design. In automatically implementing the block diagram into silicon, the SPROC programming/development environment accounts for and provides software connection and interfaces with a host microprocessor.

Abstract: A real time probe device is provided for a digital signal processor having a multiported data RAM, a time division multiplexed data RAM bus, and a processor. The probe includes a programmable comparator coupled to the address lines of the data RAM bus for determining that data is being written to a location of the multiported data RAM specified by the programmable comparator, a circuit for receiving the data on the data lines of the data RAM bus and for writing the data to a data buffer in the multiported data RAM, a reading circuit for obtaining the data from the data buffer of the multiported data RAM, and preferably a digital to analog converter for receiving at regular intervals the data obtained from the multiported data RAM and providing an analog signal therefrom. The average data rate at which data is written to the buffer in the data RAM should be the same as the rate at which data is obtained from the buffer of the data RAM for D/A conversion.