Abstract: A method includes generating samples of a grid parameter at a point of common coupling, fitting a waveform to the samples, and detecting an islanding condition in response to a parameter of the waveform. The waveform may be fit to the samples using a nonlinear algorithm. A controller includes a waveform fitting circuit to fit a waveform to samples of a grid parameter, an inverter controller to generate one or more switching signals to control an inverter in response to an error signal, and an error generator arranged to generate the error signal in response to a parameter of the waveform.

Abstract: A method of operating a switching power converter may include determining an average value of a measured parameter for substantially each switching cycle, and adjusting a control parameter during substantially each switching cycle in response to a corresponding one of the average values. In one embodiment, the control parameter comprises a switch duty cycle, and the measured parameter comprises an output current. Determining the average value of the measured parameter may include obtaining a first sample of the measured parameter during a switching cycle, and calculating the average value of the measured parameter during the switching cycle in response to the first sample.

Abstract: A power converter may include a first power path having no energy storage and a second power path having substantial energy storage. The first and second power paths have first and second input waveforms that are complementary with respect to a source waveform. The first power path, which may be more efficient than the second path, may transfer as much power as possible from the input to the output. The energy storage enables the second power path to make up the difference between the power available from the source and the power drawn by the first power path, and to make up the difference between the power demanded by a load and the power supplied by the first path.

Abstract: A power conversion system may include a controller to cause a power stage to control the flow of power to or from an energy storage device in response to a dynamic reference. The flow of power to or from the energy storage device may be controlled at a substantially higher speed than power fluctuations in a power source or load. In a power conversion system, a model including an energy storage device may be generated in real-time, and a condition of the energy storage device may be determined in response to the model.

Abstract: A signal processing system may include a multiply-accumulate (MAC) unit to generate output data by performing multiply-accumulate operations on first and second input data in response to a stream of MAC instruction words, where the MAC unit is pipelined to enable it to perform a multiply-accumulate operation in response to each MAC instruction word. The system may also include an instruction generator to generate the stream of MAC instruction words by performing loop expansion on a stream of intermediate instruction words, where one intermediate instruction word may comprise a group of fields to set up the MAC unit to execute in response to the one intermediate instruction word.

Abstract: One embodiment relates to a method for generating a periodic function in response to an argument in a digital signal processing system, where the periodic function can be represented as functions of two or more components of the argument. The method may include: obtaining a first operand from one of two or more lookup tables in response to a first component of the argument; obtaining a second operand from one of the lookup tables in response to a second component of the argument; conditionally mirroring the first and second operands in response to a quadrant of the argument; and calculating a value of the periodic function in response to the operands with a linear algebra unit without using conditional code execution.

Abstract: A method and apparatus for electronic image processing are described. One embodiment includes a method of resizing an electronic image that includes image data in two dimensions. The method includes memory-to-memory processing with separable x and y processing. Processing occurs in one or more memory-to-memory passes. On each pass, processing can be one of: low-pass filtering; low-pass filtering and decimation by two; and resampling. Processing is configurable independently in each dimension. Filters are configured on each pass and in each dimension to low-pass filter or obtain gradients for resampling. A multiplexor selects resampling or low-pass filtering on each pass.

Abstract: Systems and methods are provided for writing code to access data arrays. One aspect provides a method of accessing a memory array. Data is provided within a one-dimensional array of allocated memory. A dimensional dynamic overlay is declared from within a block of statements, and the declaration initializes various attributes within an array attribute storage object. The data is accessed from within the block of statements as a dimensional indexed array using the array attribute storage object. Another aspect provides a method of creating and accessing a dimensional dynamic array. A dimensional dynamic array is declared from within a block of statements, and memory storage for the array is dynamically allocated. A dynamic overlay storage object is also provided and its attributes are initialized from the dynamic array declaration. The data is accessed as a dimensional indexed array from within the block of statements using the array attribute storage object.

Abstract: Systems and methods are provided for caching dynamic arrays. According to one aspect, a cache memory device is provided for caching dynamic arrays or dynamic overlays. According to one embodiment, the device includes a plurality of memory cells and at least one register for storing access information to access at least one array stored in the plurality of memory cells. According to another aspect, an electronic system is provided that includes a main memory, a dynamic array cache memory device, a general cache memory device, and a processor. The dynamic array cache memory device is coupled to the main memory and adapted for caching array data. The general cache memory device is coupled to the main memory and is adapted for caching regular data. The processor is coupled to and adapted for communication with the main memory, the general cache memory device, and the dynamic array cache memory device.

Abstract: A method and system for calculating resample output values from input samples and their associated sample values. A resampling circuit calculates a frequency value for a sine-wave model from a sample set of the input samples and determines whether the frequency value is in a frequency range. In the case where the frequency value is in the frequency range, a sinusoidal transition model is determined based on the sample set. However, if the frequency value is outside of the frequency range, a non-sinusoidal model is determined based on the sample set. The resampling circuit then calculates resample output values from the resulting sinusoidal or non-sinusoidal model.

Abstract: A method and apparatus for electronic image processing are described. One embodiment includes a method of resizing an electronic image that includes image data in two dimensions. The method includes memory-to-memory processing with separable x and y processing. Processing occurs in one or more memory-to-memory passes. On each pass, processing can be one of: low-pass filtering; low-pass filtering and decimation by two; and resampling. Processing is configurable independently in each dimension. Filters are configured on each pass and in each dimension to low-pass filter or obtain gradients for resampling. A multiplexor selects resampling or low-pass filtering on each pass.

Abstract: An economical method of detecting and suppressing ringing artifacts during digital image resizing is presented. The economical method substitutes costly division calculations with cost effective comparator operations. The method also includes improved image sharpening when up-sampling an image.

Abstract: An economical method of detecting and suppressing ringing artifacts during digital image resizing is presented. The economical method substitutes costly division calculations with cost effective comparator operations. The method also includes improved image sharpening when up-sampling an image.

Abstract: A linearity corrector is provided that reduces distortion in a signal processing system, such as an ADC. The linearity corrector provides a first order signal path having distortion components connected to an adder, and a filter product circuit that is also connected to the adder. A method is provided for reducing distortion by calculating a filter product and adding the filter product to a first order signal having a relative delay such that the filter product reduces, or eliminates, the order of distortions corresponding to the order of the filter product.

Abstract: A calibration system for calibrating a linearity corrector using the sum of filter products is proved, along with a method of calibrating the linearity corrector. The calibration system includes a first and second signal generator for introducing test signals into a signal processing system, such as an ADC. An acquisition memory and processor are provided for acquiring and analyzing the output of the signal processing system and then programming the filter coefficients into the linearity corrector. The method of calibration analyzes acquired intermodulation and harmonic components from the signal processing system and then finds the amplitude and phase response for the filters. The amplitude and phase response is then used to determine a set of filter coefficients.

Abstract: A method and apparatus for electronic image processing are described. One embodiment includes a method of resizing an electronic image that includes image data in two dimensions. The method includes memory-to-memory processing with separable x and y processing. Processing occurs in one or more memory-to-memory passes. On each pass, processing can be one of: low-pass filtering; low-pass filtering and decimation by two; and resampling. Processing is configurable independently in each dimension. Filters are configured on each pass and in each dimension to low-pass filter or obtain gradients for resampling. A multiplexor selects resampling or low-pass filtering on each pass.

Abstract: A resampling circuit and method where input sample values for samples arranged along a row of a source image are received by a row resampling circuit. The row resampling circuit calculates row output values which are provided to a column resampling circuit that calculates output sample values therefrom. The column resampling circuit includes a shift register that receives the row output values and shifts the row output values through the shift register as the row output samples are calculated. The shift register has a plurality of evenly spaced sample output terminals from which the row output values are sampled by an interpolation circuit for calculation of the output sample values.

Abstract: A dither system for a quantizing device, such as a multi-stage pipelined analog-to-digital converter (ADC), derives a dither signal from a clock signal having a sample frequency, the dither signal having a frequency that is one-third of the sample frequency. The dither signal is easily converted to analog and added at the input of the quantizing device to an analog signal to be digitized. A cancellation signal circuit generates a cosine-wave signal from a digital version of the dither signal and programmable coefficients that are a function of amplitude and phase. The cosine-wave signal is combined with the digital output signal from the quantizing device to produce a corrected digital output signal having reduced quantization distortion.

Abstract: A method and apparatus for operating a content addressable memory (CAM) and a ternary CAM (TCAM) are described including an encoding circuit for encoding an incoming CAM or TCAM word to produce an encoded CAM or TCAM word such that a one-bit mismatch between a comparand and the incoming CAM or TCAM word results in at least a M-bit mismatch between said encoded CAM or TCAM word and a similarly encoded comparand, a circuit for precharging a match line to a predetermined state before a comparison between the encoded CAM or TCAM word and said similarly encoded comparand and a memory storage location for storing the encoded CAM or TCAM word.