Patents by Inventor Keith Thomas Kwietniak

Keith Thomas Kwietniak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7060624
    Abstract: Flared and non-flared metallized deep vias having aspect ratios of about 2 or greater are provided. Blind vias have been fabricated in silicon substrates up to a depth of about 300 microns, and flared through vias have been fabricated up to about 750 microns, the approximate thickness of a silicon substrate wafer, enabling the formation of electrical connections at either or both ends of a via. In spite of the depth and high aspect ratios attainable, the etched vias are completely filled with plated copper conductor, completing the formation of deep vias and allowing fuller use of both sides of the substrate.
    Type: Grant
    Filed: August 13, 2003
    Date of Patent: June 13, 2006
    Assignee: International Business Machines Corporation
    Inventors: Panayotis Andricacos, Emanuel Israel Cooper, Timothy Joseph Dalton, Hariklia Deligianni, Daniel Guidotti, Keith Thomas Kwietniak, Michelle Leigh Steen, Cornelia Kang-I Tsang
  • Patent number: 6224690
    Abstract: An interconnection structure suitable for the connection of microelectronic circuit chips to packages is provided by this invention. In particular, the invention pertains to the area-array or flip-chip technology often called C4 (controlled collapse chip connection). The structure comprises an adhesion/barrier layer deposited on a passivated substrate (e.g., a silicon wafer), optionally an additional adhesion layer, a solderable layer of a metal selected from the group consisting of Ni, Co, Fe, NiFe, NiCo, CoFe and NiCoFe on the adhesion/barrier layer, and a lead-free solder ball comprising tin as the predominate component and one or more alloying elements selected from Bi, Ag, and Sb, and further optionally including one or more elements selected from the group consisting of Zn, In, Ni, Co and Cu.
    Type: Grant
    Filed: March 12, 1996
    Date of Patent: May 1, 2001
    Assignee: International Business Machines Corporation
    Inventors: Panayotis Constantinou Andricacos, Madhav Datta, Hariklia Deligianni, Wilma Jean Horkans, Sung Kwon Kang, Keith Thomas Kwietniak, Gangadhara Swami Mathad, Sampath Purushothaman, Leathen Shi, Ho-Ming Tong
  • Patent number: 5937320
    Abstract: The present invention provides a means of fabricating a reliable C4 flip-chip structure for low-temperature joining. The electrochemically fabricated C4 interconnection has a barrier layer between the electroplated tin-rich solder bump and the ball-limiting metallurgy that protects the terminal metal in the ball-limiting metallurgy from attack by the Sn in the solder. The barrier layer is electroplated through the same photoresist mask as the solder and thus does not require a separate patterning step. A thin layer of electroplated nickel serves as a reliable barrier layer between a copper-based ball-limiting metallurgy and a tin-lead (Sn--Pb) eutectic C4 ball.
    Type: Grant
    Filed: April 8, 1998
    Date of Patent: August 10, 1999
    Assignee: International Business Machines Corporation
    Inventors: Panayotis Constantinou Andricacos, Madhav Datta, Wilma Jean Horkans, Sung Kwon Kang, Keith Thomas Kwietniak