Abstract: An edge seal for sealing an outer surface of a lower electrode assembly configured to support a semiconductor substrate in a plasma processing chamber, the lower electrode assembly including an annular groove defined between a lower member and an upper member of the lower electrode assembly. The edge seal includes an elastomeric band configured to be arranged within the groove, the elastomeric band having an annular upper surface, an annular lower surface, an inner surface, and an outer surface. When the elastomeric band is in an uncompressed state, the outer surface of the elastomeric band is concave. When the upper and lower surfaces are axially compressed at least 1% such that the elastomeric band is in a compressed state, an outward bulging of the outer surface is not greater than a predetermined distance. The predetermined distance corresponds to a maximum outer diameter of the elastomeric band in the uncompressed state.

Abstract: An edge seal for sealing an outer surface of a lower electrode assembly configured to support a semiconductor substrate in a plasma processing chamber, the lower electrode assembly including an annular groove defined between a lower member and an upper member of the lower electrode assembly. The edge seal includes an elastomeric band configured to be arranged within the groove, the elastomeric band having an annular upper surface, an annular lower surface, an inner surface, and an outer surface. When the elastomeric band is in an uncompressed state, the outer surface of the elastomeric band is concave. When the upper and lower surfaces are axially compressed at least 1% such that the elastomeric band is in a compressed state, an outward bulging of the outer surface is not greater than a predetermined distance. The predetermined distance corresponds to a maximum outer diameter of the elastomeric band in the uncompressed state.

Abstract: A lower electrode assembly configured to support a semiconductor substrate in a plasma processing chamber includes a base plate, an upper plate above the base plate, and a mounting groove surrounding a bond layer located between the base plate and the upper plate. An edge seal including a compressible ring is mounted in the mounting groove such that the compressible ring is axially compressed between the upper plate and the base plate. At least one gas passage is in fluid communication with an annular space between the compressible ring and an inner wall of the mounting groove. The at least gas one passage extends through the base plate and includes a plurality of outlets in fluid communication with the annular space. In some examples, a backing seal may be located between the edge seal and an inner wall of the mounting groove.

Abstract: A semiconductor substrate support for supporting a semiconductor substrate in a plasma processing chamber includes a heater array comprising thermal control elements operable to tune a spatial temperature profile on the semiconductor substrate, the thermal control elements defining heater zones each of which is powered by two or more power supply lines and two or more power return lines wherein each power supply line is connected to at least two of the heater zones and each power return line is connected to at least two of the heater zones. A power distribution circuit is mated to a baseplate of the substrate support, the power distribution circuit being connected to each power supply line and power return line of the heater array. A switching device is connected to the power distribution circuit to independently provide time-averaged power to each of the heater zones by time divisional multiplexing of a plurality of switches.

Abstract: A semiconductor substrate support for supporting a semiconductor substrate in a plasma processing chamber includes a multi-plane heater such as a heater array comprising thermal control elements operable to tune a spatial temperature profile on the semiconductor substrate. The multi-plane heater includes at least one pair of vertically offset heating elements connected in series or parallel to control heating output in a heating zone on the substrate support. The thermal control elements can be powered by two or more power supply lines and two or more power return lines wherein each power supply line is connected to at least two of the heater zones and each power return line is connected to at least two of the heater zones.

Abstract: A method of determining thermal stability of an upper surface of a substrate support assembly in a plasma processing apparatus includes: before processing of at least one substrate in the plasma processing apparatus and while powering an array of thermal control elements of the substrate support assembly to achieve a desired spatial and temporal temperature of the upper surface of the substrate support assembly, recording pre-process temperature data of the substrate support assembly; after the processing of the at least one substrate in the plasma processing apparatus and while powering the array of thermal control elements to achieve the desired spatial and temporal temperature of the upper surface of the substrate support assembly, recording post-process temperature data; comparing the post-process temperature data to the pre-process temperature data; and determining whether the post-process temperature data is within a predetermined tolerance range of the pre-process temperature data.

Abstract: A system for controlling a temperature of a wafer processing substrate includes memory that stores first data indicative of first temperature responses of at least one first thermal control element. The first data corresponds to the first temperature responses as observed when a first control parameter of the at least one first thermal control element is maintained at a first predetermined first value. A first controller receives a setpoint temperature for the wafer processing substrate and maintains the first control parameter of the at least one first thermal control element at a second value based on the received setpoint temperature. A second controller retrieves the first data from the memory, calculates second data indicative of temperature non-uniformities associated with the wafer processing substrate based on the first data and the second value, and controls a plurality of second thermal control elements based on the calculated second data.

Abstract: A semiconductor substrate support for supporting a semiconductor substrate in a plasma processing chamber includes a heater array comprising thermal control elements operable to tune a spatial temperature profile on the semiconductor substrate, the thermal control elements defining heater zones each of which is powered by two or more power supply lines and two or more power return lines wherein each power supply line is connected to at least two of the heater zones and each power return line is connected to at least two of the heater zones. A power distribution circuit is mated to a baseplate of the substrate support, the power distribution circuit being connected to each power supply line and power return line of the heater array. A switching device is connected to the power distribution circuit to independently provide time-averaged power to each of the heater zones by time divisional multiplexing of a plurality of switches.

Abstract: A lower electrode assembly configured to support a semiconductor substrate in a plasma processing chamber includes a base plate, an upper plate above the base plate, and a mounting groove surrounding a bond layer located between the base plate and the upper plate. An edge seal including a compressible ring is mounted in the mounting groove such that the compressible ring is axially compressed between the upper plate and the base plate. At least one gas passage is in fluid communication with an annular space between the compressible ring and an inner wall of the mounting groove. The at least gas one passage extends through the base plate and includes a plurality of outlets in fluid communication with the annular space. In some examples, a backing seal may be located between the edge seal and an inner wall of the mounting groove.

Abstract: A lower electrode assembly useful for supporting a semiconductor substrate in a plasma processing chamber includes a temperature controlled base plate, an upper plate above the base plate, and an annular mounting groove surrounding a bond layer located between the base plate and the upper plate. The mounting groove includes an inner wall, an opening of the mounting groove faces radially outward relative to the inner wall, and the mounting groove includes a step extending downward from the upper plate on an upper wall of the groove or extending upward from the base plate on a lower wall of the groove. An edge seal including a compressible ring is mounted in the groove such that the compressible ring is compressed between the upper plate and the base plate to cause an outer surface of the compressible ring to be biased radially outward relative to the inner wall toward the step.

Abstract: A plasma etching system having a substrate support assembly with multiple independently controllable heater zones. The plasma etching system is configured to control etching temperature of predetermined locations so that pre-etch and/or post-etch non-uniformity of critical device parameters can be compensated for.

Abstract: A semiconductor substrate support for supporting a semiconductor substrate in a plasma processing chamber includes a heater array comprising thermal control elements operable to tune a spatial temperature profile on the semiconductor substrate, the thermal control elements defining heater zones each of which is powered by two or more power supply lines and two or more power return lines wherein each power supply line is connected to at least two of the heater zones and each power return line is connected to at least two of the heater zones. A power distribution circuit is mated to a baseplate of the substrate support, the power distribution circuit being connected to each power supply line and power return line of the heater array. A switching device is connected to the power distribution circuit to independently provide time-averaged power to each of the heater zones by time divisional multiplexing of a plurality of switches.

Abstract: An edge seal for sealing an outer surface of a lower electrode assembly configured to support a semiconductor substrate in a plasma processing chamber, the lower electrode assembly including an annular groove defined between a lower member and an upper member of the lower electrode assembly. The edge seal includes an elastomeric band configured to be arranged within the groove, the elastomeric band having an annular upper surface, an annular lower surface, an inner surface, and an outer surface. When the elastomeric band is in an uncompressed state, the outer surface of the elastomeric band is concave. When the upper and lower surfaces are axially compressed at least 1% such that the elastomeric band is in a compressed state, an outward bulging of the outer surface is not greater than a predetermined distance. The predetermined distance corresponds to a maximum outer diameter of the elastomeric band in the uncompressed state.

Abstract: A lower electrode assembly useful for supporting a semiconductor substrate in a plasma processing chamber includes a temperature controlled lower base plate, an upper plate, a mounting groove surrounding a bond layer and an edge seal comprising an elastomeric band having an outer concave surface in an uncompressed state, the band mounted in the groove such that upper and lower ends of the band are axially compressed and a maximum outward bulging of the band is no greater than a predetermined distance.

Abstract: A lower electrode assembly useful for supporting a semiconductor substrate in a plasma processing chamber includes a temperature controlled lower base plate, an upper plate, a mounting groove surrounding a bond layer and an edge seal comprising an elastomeric band having an outer concave surface in an uncompressed state, the band mounted in the groove such that upper and lower ends of the band are axially compressed and a maximum outward bulging of the band is no greater than a predetermined distance.

Abstract: A method of determining thermal stability of an upper surface of a substrate support assembly in a plasma processing apparatus includes: before processing of at least one substrate in the plasma processing apparatus and while powering an array of thermal control elements of the substrate support assembly to achieve a desired spatial and temporal temperature of the upper surface of the substrate support assembly, recording pre-process temperature data of the substrate support assembly; after the processing of the at least one substrate in the plasma processing apparatus and while powering the array of thermal control elements to achieve the desired spatial and temporal temperature of the upper surface of the substrate support assembly, recording post-process temperature data; comparing the post-process temperature data to the pre-process temperature data; and determining whether the post-process temperature data is within a predetermined tolerance range of the pre-process temperature data.

Abstract: A method of determining thermal stability of an upper surface of a substrate support assembly comprises recording time resolved pre-process temperature data of the substrate before performing a plasma processing process while powering an array of thermal control elements to achieve a desired spatial and temporal temperature of the upper surface. A substrate is processed while powering the array of thermal control elements to achieve a desired spatial and temporal temperature of the upper surface of the assembly, and time resolved post-process temperature data of the assembly is recorded after processing the substrate. The post-process temperature data is recorded while powering the thermal control elements to achieve a desired spatial and temporal temperature of the upper surface. The post-process temperature data is compared to the pre-process temperature data to determine whether the data is within a desired tolerance range.

Abstract: A semiconductor substrate support for supporting a semiconductor substrate in a plasma processing chamber includes a multi-plane heater such as a heater array comprising thermal control elements operable to tune a spatial temperature profile on the semiconductor substrate. The multi-plane heater includes at least one pair of vertically offset heating elements connected in series or parallel to control heating output in a heating zone on the substrate support. The thermal control elements can be powered by two or more power supply lines and two or more power return lines wherein each power supply line is connected to at least two of the heater zones and each power return line is connected to at least two of the heater zones.

Abstract: A method for auto-correction of at least one malfunctioning thermal control element among an array of thermal control elements that are independently controllable and located in a temperature control plate of a substrate support assembly which supports a semiconductor substrate during processing thereof, the method including: detecting, by a control unit including a processor, that at least one thermal control element of the array of thermal control elements is malfunctioning; deactivating, by the control unit, the at least one malfunctioning thermal control element; and modifying, by the control unit, a power level of at least one functioning thermal control element in the temperature control plate to minimize impact of the malfunctioning thermal control element on the desired temperature output at the location of the at least one malfunctioning thermal control element.

Abstract: A chuck includes a first material layer having an upper surface upon which a wafer is supported. The upper surface includes portions that physically contact the wafer and portions that form gaps between the upper surface and the wafer. The chuck also includes a second material layer defined to support the first material layer. The second material layer is formed of a thermally conductive material and includes a first number of channels. The chuck also includes a second number of channels defined to direct a gas to portions of the upper surface that form gaps between the upper surface and the wafer. The chuck is characterized by a thermal calibration curve that represents a thermal interface between the upper surface and the wafer, heat transfer through the first material layer to the second material layer, and heat transfer through the second material layer to the first number of channels.