Abstract: According to one embodiment, a server has a first storage, a second storage, a built-in business form modification part, download execution part, and search part. The download execution part transmits the objective business form and the business form generation program stored in the first and second storage to a user terminal. The search part searches for the plant data in response to a request from the user terminal and transmits the data to the terminal. The business form generation program includes a business form definition program and a data expansion program. The business form definition program sets search conditions of plant data in the objective business form. The data expansion program requests the server to search for the plant data that satisfies the search conditions in the objective business form and outputs the plant data to the objective business form. The user terminal has an objective business form editing part and a business form generation part.

Abstract: In the peripheral area of a semiconductor chip 10A, there is arranged a macro cell 51 which comprises a fuse circuit having a plurality of fuse circuit units, each of which has a fuse and outputs a signal indicating whether or not the fuse is cut off, and a predecoder receiving the outputs of the fuse circuit. In the interior of the chip 10A, there is arranged a macro cell 41 which comprises a main decoder 33 receiving the outputs of the predecoder, a signal conversion circuit 34 for converting the outputs of the main decoder 33 to generate a conversion signal, and a memory circuit 20. The memory circuit 20 comprises a plurality of normal memory blocks and a redundant memory block with the same configuration to each other, and a switching circuit for, in response to the conversion signal, making a defect one of the normal memory blocks out of use with making the redundant memory block in use.

Abstract: In the peripheral area of a semiconductor chip 10A, there is arranged a macro cell 51 which comprises a fuse circuit having a plurality of fuse circuit units, each of which has a fuse and outputs a signal indicating whether or not the fuse is cut off, and a predecoder receiving the outputs of the fuse circuit. In the interior of the chip 10A, there is arranged a macro cell 41 which comprises a main decoder 33 receiving the outputs of the predecoder, a signal conversion circuit 34 for converting the outputs of the main decoder 33 to generate a conversion signal, and a memory circuit 20. The memory circuit 20 comprises a plurality of normal memory blocks and a redundant memory block with the same configuration to each other, and a switching circuit for, in response to the conversion signal, making a defect one of the normal memory blocks out of use with making the redundant memory block in use.

Abstract: A multiport memory that allows simultaneous reading and/or writing to the same memory cells by shorting selected bit lines with other bit lines of cells whose row address from each port match.

Abstract: A dual-port memory circuit includes a memory cell having a pair of nodes, a first port having a first pair of bit lines and a first word line connected to said memory cell, and a second port having a second pair of bit lines and a second word line connected to said memory cell. A detection circuit detects that data is written from one of the first and second ports in a state where the memory cell is selected by both the first and second ports. A control circuit decreases a potential of one of the nodes in response to a detection output of the detection circuit.

Abstract: In a one-directional internal circuit such as a first-in first-out (FIFO), switchover switches are provided between the internal input/output ports and external ports thereof, and the switches are controlled by a mode signal, thereby enabling a bidirectional data transmission within one chip.

Abstract: In a dual port type semiconductor memory device (FIFO), a register is provided between a read side of a memory cell array and a data output. When data is read from the memory cell array to the data output, a content stored in the memory cell array is transmitted in advance by a preceding read instruction clock to the register, thereby enhancing the read operation speed.

Abstract: A static-type semiconductor memory device having a three-layer structure: gate-electrode wiring lines being formed from a first conductive layer of, for example, polycrystalline silicon; word lines, ground lines, and power supply lines being formed from a second conductive layer of, for example, aluminum; and bit lines being formed from a third conductive layer of, for example, aluminum. The bit lines extending in a column direction, and the ground lines extending in a row direction. Thus, providing an improved degree of integration, an improved operating speed, an improved manufacturing yield, and a countermeasure for soft errors due to alpha particles.

Abstract: A semiconductor memory device having data buses for connecting memory cells in memory cell arrays with input/output buffer circuit includes a plurality of memory cell arrays having repetitive patterns. In the device, a plurality of column decoders are adjacent to the memory cell arrays and have repetitive patterns. A portion of the column decoders is displaced from a regular location in the column decoder to a separate location on a substrate of the semiconductor memory device to leave a blank portion in the column decoder. The device also includes an input/output buffer circuit, data buses for connecting the memory cell arrays to the corresponding input/output buffer circuit through spaces outside the column decoders including the blank portion, and conductors for connecting the displaced portion of column decoders located in the separate location to the corresponding memory cell arrays through spaces outside the column decoders including the blank portion.

Abstract: An asynchronous semiconductor memory device having an address change detector which generates a pulse with a specified pulse width by detecting change in an address signal and a component for holding an internal circuit in the non-operating condition responding to the address signal for a period when said pulse does not exist. The internal circuit is caused not to operate in response to an unwanted address signal generated in the course of the change of the address signal input from an external device, or in response to an unwanted address signal generated by noise. Thereby power consumption is reduced.

Abstract: A semiconductor memory device, whose pairs of bit lines are connected to a pair of data buses, are divided into a plurality of blocks each comprising a plurality of parted memory cells, a pair of switching elements, and a block sense amplifier. The block sense amplifier has different driving abilities respectively so that the sense amplifier in the farthest block from the data bus has the most driving ability, the sense amplifier in the block nearer to the data bus has less driving ability, and the sense amplifier in the nearest block to the data bus has the least sensing ability. There is only one sense amplifier activated in a selected block, which is a block having a memory cell to be accessed. The operation of the pair of switching elements in a respective block is made after the sense amplifier in the selected block is activated so that the pairs of switching elements in the selected block and the blocks closer to the data bus looking from the selected block are turned ON.

Abstract: A semiconductor device having a circuit for regulating the external power supply voltage applied to the chip. When numerous chips are used in an electronic circuit having an external power supply voltage, variations in the electrical characteristics, such as the total power supply current, of each chip, become a problem. According to the present invention, variations in the electrical characteristics can be reduced by compensating the chip-to-chip fluctuations of the conductance of transistors (FETs) contained in an inner circuit disposed on the chip. A dummy transistor having a relatively short channel length is employed as a circuit for detecting the electrical characteristics of the transistors formed on the chip. The voltage drop across the dummy transistor is employed as a representative signal since it is sensitive to variations in the characteristics of the FETs contained in the inner circuit.

Abstract: A organization for multi-bit output includes a plurality of memory cell groups and a plurality of data buses, each of which belongs to each of the groups, wherein one of memory cells in each memory cell groups are selected at the same time. A semiconductor memory device includes a plurality of groups of redundant cells one of which can replace a group of memory cells which comprise a defective memory cell, and switching circuits which selectively connect one of the groups of the redundant cells to the data bus belonging to one of the groups of memory cells. The switching circuit can connect the one of groups of the redundant cells to one of the data buses belonging to any of the cell groups.

Abstract: A semiconductor memory device includes at least a pair of bit lines, a word line, a pair of load transistors each connected to the bit lines, a memory cell connected to the bit lines and the word line and selected by an address signal, and an equalizing circuit connected between each of the bit lines. According to the present invention, the equalizing circuit comprises an P-channel type MIS transistor and an N-channel type MIS transistor that are connected in parallel and temporarily turned ON in response to a change of the address signal.

Abstract: A static memory circuit includes memory cells arranged in a matrix of word lines and bit lines, and a reset circuit for resetting each pair of bit lines to have an equivalent potential in response to a change in a row address signal. The reset circuit generates a reset signal at a first time a certain time period after a first change of the row address signal and terminates the reset signal at a second time when a second change of the row address signal is detected. Thus, data destruction during reading is prevented.

Abstract: A semiconductor memory device in which the memory cells are arranged in matrix form and in which, when a defective cell exists among the memory cells and a row or column containing the defective cell is selected, the selected row or column is switched to a predetermined redundant row or a predetermined redundant column additionally and independently provided. A plurality of switching circuits are provided, each of the switching circuits being connected to the output of the decoder circuit, which select the row or the column of memory cells. A fusing circuit is connected to each of the switching circuits, and when the fuse in the fusing circuit is disconnected, the row or the column containing the defective cell is switched to the redundant row or the redundant column.

Abstract: The present invention reduces rising and/or falling time delay of digital signals on poly-silicon layer wiring lines in semiconductors. Specific points of a network are fed with positive or negative voltage from a power source immediately after the initial rise and/or fall of the digital signals, and the potential at the specific point is rapidly pulled up or pulled down toward the source voltage. The pulling by the power source voltage is stopped when the potential reaches a specified value, and the pull-up or pull-down does not prevent subsequent operations. The signals reform or restore a square wave shape to the digital signals. The circuit includes a positive feedback circuit and a positive feedback cut-off circuit, each comprising an inverter and a transistor.

Abstract: In a static semiconductor memory device incorporating redundancy memory cells (C.sub.R0, C.sub.R1, . . . ), a connecting/disconnecting circuit is linked between a power supply terminal (V.sub.CC) and one of bit lines (B.sub.0, B.sub.0, . . . ), thereby reducing or cutting off a current flowing through a defective memory cell.

Abstract: A CMIS circuit device such as an IC chip in a semiconductor memory device, is made selectable by using at least two chip-select signals having opposite polarities. The CMIS circuit device has a chip-select control circuit for establishing a chip-selected state or a chip-unselected state upon receiving the abovementioned chip-select signals. The chip-select control circuit includes a CMIS inverter circuit which inverts one of the chip-select signals, and a CMIS logic gate circuit which receives an output signal from the CMIS inverter circuit and the other chip select signal or signals and outputs an internal chip-select control signal. The CMIS inverter circuit includes a CMIS inverter and one or more control transistors which receive the other chip-select signal or signals at the gates thereof and which are inserted in series between a power terminal of the CMIS inverter and a power source.

Abstract: A semiconductor memory circuit including a pair of feedback means. The feedback means are connected between pairs of conventional bit lines and control gates of conventional load transistors. The feedback means control the on or off state of these load transistors in accordance with the logic states of the pair of bit lines.