Patents by Inventor Kelin Kuhn
Kelin Kuhn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11996129Abstract: A semiconductor device includes ferromagnetic, magnetostrictive layer that exhibits a biaxial magnetic anisotropy and an underlying structure exhibits a spin Hall effect to provide a conversion between electrical energy and magnetic energy with more than two distinctive magnetic states, wherein the underlying structure includes a piezoelectric material structure and a spin Hall metal layer.Type: GrantFiled: June 12, 2017Date of Patent: May 28, 2024Assignees: Cornell University, The Curators of the University of Missouri, The Regents of the University of Michigan, Oregon State UniversityInventors: Darrell Schlom, Mostafizur Rahman, Kelin Kuhn, John Heron
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Publication number: 20230186961Abstract: This patent document provides implementations and examples of circuits and devices based on low-energy consumption semiconductor structures exhibiting multi-valued states. In one aspect, a semiconductor device is configured to comprise: a multi-layer structure forming a magnetoelectric or multiferroic system to include a ferromagnetic, magnetostrictive layer that exhibits a biaxial magnetic anisotropy and an underlying metal structure exhibits a spin Hall effect to provide a conversion between electrical energy and magnetic energy with more than two distinctive magnetic states.Type: ApplicationFiled: June 12, 2017Publication date: June 15, 2023Inventors: Darrell Schlom, Mostafizur Rahman, Kelin Kuhn, John Heron
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Patent number: 10121861Abstract: A nanowire device of the present description may be produced with the incorporation of at least one hardmask during the fabrication of at least one nanowire transistor in order to assist in protecting an uppermost channel nanowire from damage that may result from fabrication processes, such as those used in a replacement metal gate process and/or the nanowire release process. The use of at least one hardmask may result in a substantially damage free uppermost channel nanowire in a multi-stacked nanowire transistor, which may improve the uniformity of the channel nanowires and the reliability of the overall multi-stacked nanowire transistor.Type: GrantFiled: March 15, 2013Date of Patent: November 6, 2018Assignee: Intel CorporationInventors: Seung Hoon Sung, Seiyon Kim, Kelin Kuhn, Willy Rachmady, Jack Kavalieros
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Patent number: 10115822Abstract: Methods of forming a strained channel device utilizing dislocations disposed in source/drain structures are described. Those methods/structures may include forming a source/drain region in a substrate of a device, and forming an alloy in the source/drain region, wherein the alloy comprises a material that decreases a band gap between source/drain contacts and the source/drain regions to substantially zero. The embodiments herein reduce an external parasitic resistance of the device.Type: GrantFiled: September 26, 2013Date of Patent: October 30, 2018Assignee: Intel CorporationInventors: Rafael Rios, Roza Kotlyar, Kelin Kuhn
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Patent number: 9947805Abstract: Nanowire-based mechanical switching devices are described. For example, a nanowire relay includes a nanowire disposed in a void disposed above a substrate. The nanowire has an anchored portion and a suspended portion. A first gate electrode is disposed adjacent the void, and is spaced apart from the nanowire. A first conductive region is disposed adjacent the first gate electrode and adjacent the void, and is spaced apart from the nanowire.Type: GrantFiled: May 10, 2016Date of Patent: April 17, 2018Assignee: Intel CorporationInventors: Chytra Pawashe, Kevin Lin, Anurag Chaudhry, Raseong Kim, Seiyon Kim, Kelin Kuhn, Sasikanth Manipatruni, Rafael Rios, Ian A. Young
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Patent number: 9825130Abstract: A nanowire device of the present description may include a highly doped underlayer formed between at least one nanowire transistor and the microelectronic substrate on which the nanowire transistors are formed, wherein the highly doped underlayer may reduce or substantially eliminate leakage and high gate capacitance which can occur at a bottom portion of a gate structure of the nanowire transistors. As the formation of the highly doped underlayer may result in gate inducted drain leakage at an interface between source structures and drain structures of the nanowire transistors, a thin layer of undoped or low doped material may be formed between the highly doped underlayer and the nanowire transistors.Type: GrantFiled: March 14, 2013Date of Patent: November 21, 2017Assignee: Intel CorporationInventors: Seiyon Kim, Kelin Kuhn, Rafael Rios, Mark Armstrong
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Patent number: 9614060Abstract: A nanowire device of the present description may be produced with the incorporation of at least one underlayer etch stop formed during the fabrication of at least one nanowire transistor in order to assist in protecting source structures and/or drain structures from damage that may result from fabrication processes. The underlayer etch stop may prevent damage to the source structures and/or drain the structures, when the material used in the fabrication of the source structures and/or the drain structures is susceptible to being etched by the processes used in the removal of the sacrificial materials, i.e. low selectively to the source structure and/or the drain structure materials, such that potential shorting between the transistor gate electrodes and contacts formed for the source structures and/or the drain structures may be prevented.Type: GrantFiled: June 6, 2016Date of Patent: April 4, 2017Assignee: Intel CorporationInventors: Seiyon Kim, Daniel Aubertine, Kelin Kuhn, Anand Murthy
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Publication number: 20160329438Abstract: Nanowire-based mechanical switching devices are described. For example, a nanowire relay includes a nanowire disposed in a void disposed above a substrate. The nanowire has an anchored portion and a suspended portion. A first gate electrode is disposed adjacent the void, and is spaced apart from the nanowire. A first conductive region is disposed adjacent the first gate electrode and adjacent the void, and is spaced apart from the nanowire.Type: ApplicationFiled: May 10, 2016Publication date: November 10, 2016Inventors: Chytra Pawashe, Kevin Lin, Anurag Chaudhry, Raseong Kim, Seiyon Kim, Kelin Kuhn, Sasikanth Manipatruni, Rafael Rios, Ian A. Young
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Publication number: 20160284821Abstract: A nanowire device of the present description may be produced with the incorporation of at least one underlayer etch stop formed during the fabrication of at least one nanowire transistor in order to assist in protecting source structures and/or drain structures from damage that may result from fabrication processes. The underlayer etch stop may prevent damage to the source structures and/or drain the structures, when the material used in the fabrication of the source structures and/or the drain structures is susceptible to being etched by the processes used in the removal of the sacrificial materials, i.e. low selectively to the source structure and/or the drain structure materials, such that potential shorting between the transistor gate electrodes and contacts formed for the source structures and/or the drain structures may be prevented.Type: ApplicationFiled: June 6, 2016Publication date: September 29, 2016Applicant: Intel CorporationInventors: Seiyon Kim, Daniel Aubertine, Kelin Kuhn, Anand Murthy
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Patent number: 9385221Abstract: A nanowire device of the present description may be produced with the incorporation of at least one underlayer etch stop formed during the fabrication of at least one nanowire transistor in order to assist in protecting source structures and/or drain structures from damage that may result from fabrication processes. The underlayer etch stop may prevent damage to the source structures and/or drain the structures, when the material used in the fabrication of the source structures and/or the drain structures is susceptible to being etched by the processes used in the removal of the sacrificial materials, i.e. low selectively to the source structure and/or the drain structure materials, such that potential shorting between the transistor gate electrodes and contacts formed for the source structures and/or the drain structures may be prevented.Type: GrantFiled: April 16, 2015Date of Patent: July 5, 2016Assignee: Intel CorporationInventors: Seiyon Kim, Daniel Aubertine, Kelin Kuhn, Anand Murthy
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Publication number: 20160181424Abstract: Methods of forming a strained channel device utilizing dislocations disposed in source/drain structures are described. Those methods/structures may include forming a source/drain region in a substrate of a device, and forming an alloy in the source/drain region, wherein the alloy comprises a material that decreases a band gap between source/drain contacts and the source/drain regions to substantially zero. The embodiments herein reduce an external parasitic resistance of the device.Type: ApplicationFiled: September 26, 2013Publication date: June 23, 2016Applicant: Intel CorporationInventors: Rafael RIOS, Roza KOTLYAR, Kelin KUHN
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Patent number: 9362074Abstract: Nanowire-based mechanical switching devices are described. For example, a nanowire relay includes a nanowire disposed in a void disposed above a substrate. The nanowire has an anchored portion and a suspended portion. A first gate electrode is disposed adjacent the void, and is spaced apart from the nanowire. A first conductive region is disposed adjacent the first gate electrode and adjacent the void, and is spaced apart from the nanowire.Type: GrantFiled: March 14, 2013Date of Patent: June 7, 2016Assignee: Intel CorporationInventors: Chytra Pawashe, Kevin Lin, Anurag Chaudhry, Raseong Kim, Seiyon Kim, Kelin Kuhn, Sasikanth Manipatruni, Rafael Rios, Ian A. Young
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Publication number: 20150221744Abstract: A nanowire device of the present description may be produced with the incorporation of at least one underlayer etch stop formed during the fabrication of at least one nanowire transistor in order to assist in protecting source structures and/or drain structures from damage that may result from fabrication processes. The underlayer etch stop may prevent damage to the source structures and/or drain the structures, when the material used in the fabrication of the source structures and/or the drain structures is susceptible to being etched by the processes used in the removal of the sacrificial materials, i.e. low selectively to the source structure and/or the drain structure materials, such that potential shorting between the transistor gate electrodes and contacts formed for the source structures and/or the drain structures may be prevented.Type: ApplicationFiled: April 16, 2015Publication date: August 6, 2015Applicant: Intel CorporationInventors: Seiyon Kim, Daniel Aubertine, Kelin Kuhn, Anand Murthy
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Patent number: 9064944Abstract: A nanowire device of the present description may be produced with the incorporation of at least one underlayer etch stop formed during the fabrication of at least one nanowire transistor in order to assist in protecting source structures and/or drain structures from damage that may result from fabrication processes. The underlayer etch stop may prevent damage to the source structures and/or drain the structures, when the material used in the fabrication of the source structures and/or the drain structures is susceptible to being etched by the processes used in the removal of the sacrificial materials, i.e. low selectively to the source structure and/or the drain structure materials, such that potential shorting between the transistor gate electrodes and contacts formed for the source structures and/or the drain structures may be prevented.Type: GrantFiled: March 15, 2013Date of Patent: June 23, 2015Assignee: Intel CorporationInventors: Seiyon Kim, Daniel Aubertine, Kelin Kuhn, Anand Murthy
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Publication number: 20150129830Abstract: A nanowire device of the present description may be produced with the incorporation of at least one hardmask during the fabrication of at least one nanowire transistor in order to assist in protecting an uppermost channel nanowire from damage that may result from fabrication processes, such as those used in a replacement metal gate process and/or the nanowire release process. The use of at least one hardmask may result in a substantially damage free uppermost channel nanowire in a multi-stacked nanowire transistor, which may improve the uniformity of the channel nanowires and the reliability of the overall multi-stacked nanowire transistor.Type: ApplicationFiled: March 15, 2013Publication date: May 14, 2015Inventors: Seung Hoon Sung, Kelin Kuhn, Seiyon Kim, Jack Kavalieros, Willy Rachmady
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Publication number: 20140264280Abstract: A nanowire device of the present description may be produced with the incorporation of at least one underlayer etch stop formed during the fabrication of at least one nanowire transistor in order to assist in protecting source structures and/or drain structures from damage that may result from fabrication processes. The underlayer etch stop may prevent damage to the source structures andor drain the structures, when the material used in the fabrication of the source structures andor the drain structures is susceptible to being etched by the processes used in the removal of the sacrificial materials, i.e. low selectively to the source structure and/or the drain structure materials, such that potential shorting between the transistor gate electrodes and contacts formed for the source structures andor the drain structures may be prevented.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Inventors: Seiyon Kim, Daniel Aubertine, Kelin Kuhn, Anand Murthy
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Publication number: 20140262707Abstract: Nanowire-based mechanical switching devices are described. For example, a nanowire relay includes a nanowire disposed in a void disposed above a substrate. The nanowire has an anchored portion and a suspended portion. A first gate electrode is disposed adjacent the void, and is spaced apart from the nanowire. A first conductive region is disposed adjacent the first gate electrode and adjacent the void, and is spaced apart from the nanowire.Type: ApplicationFiled: March 14, 2013Publication date: September 18, 2014Inventors: Chytra Pawashe, Kevin Lin, Anurag Chaudhry, Raseong Kim, Seiyon Kim, Kelin Kuhn, Sasikanth Manipatruni, Rafael Rios, Ian A. Young
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Publication number: 20140264253Abstract: A nanowire device of the present description may include a highly doped underlayer formed between at least one nanowire transistor and the microelectronic substrate on which the nanowire transistors are formed, wherein the highly doped underlayer may reduce or substantially eliminate leakage and high gate capacitance which can occur at a bottom portion of a gate structure of the nanowire transistors. As the formation of the highly doped underlayer may result in gate inducted drain leakage at an interface between source structures and drain structures of the nanowire transistors, a thin layer of undoped or low doped material may be formed between the highly doped underlayer and the nanowire transistors.Type: ApplicationFiled: March 14, 2013Publication date: September 18, 2014Inventors: Seiyon Kim, Kelin Kuhn, Rafael Rios, Mark Armstrong
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Patent number: 8487348Abstract: The present disclosure relates to the field of fabricating microelectronic devices. In at least one embodiment, the present disclosure relates to forming isolation structures in strained semiconductor bodies of non-planar transistors while maintaining strain in the semiconductor bodies.Type: GrantFiled: August 17, 2012Date of Patent: July 16, 2013Assignee: Intel CorporationInventors: Stephen M. Cea, Martin D. Giles, Kelin Kuhn, Jack T. Kavalieros, Markus Kuhn
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Publication number: 20120305990Abstract: The present disclosure relates to the field of fabricating microelectronic devices. In at least one embodiment, the present disclosure relates to forming isolation structures in strained semiconductor bodies of non-planar transistors while maintaining strain in the semiconductor bodies.Type: ApplicationFiled: August 17, 2012Publication date: December 6, 2012Inventors: Stephen M Cea, Martin D. Giles, Kelin Kuhn, Jack T. Kavalieros, Markus Kuhn