Abstract: In one example, a method comprises: receiving a voltage from a power converter, and generating a comparison result representing a comparison between the voltage and a voltage threshold. The method further comprises providing one of a first current reference or a second current reference to the power converter responsive to the comparison result, in which the first and second current references represent different current levels.

Abstract: A voltage detector comprises an input, a resistor divider circuit having resistors coupled in series with one another between the input and a reference node, and N intermediate nodes joining adjacent pairs of the resistors. The voltage detector has N switches coupled to the respective intermediate nodes, as well as a comparator with an input coupled to the switches, a state machine having an input coupled to the output of the comparator, and a decoder having N decoder outputs coupled to respective control terminals of the N switches.

Abstract: A DC-DC regulator system includes a power circuit which has a first input coupled to receive an input voltage, a second input coupled to receive a control signal and an output to provide a regulated output voltage. The system includes a control circuit which has a first input coupled to receive the regulated output voltage, a second input coupled to receive a reference voltage, a first output to provide the control signal, and a second output to provide a converter clock signal. The system includes an out-of-audio circuit which has a first input coupled to receive a minimum threshold frequency signal, a second input coupled to receive the converter clock signal, a third input coupled to the power circuit output, and a fourth input coupled to receive a bandwidth control clock signal.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for temperature insensitive voltage supervisors. An example apparatus includes a PTAT generation circuit including an output terminal: a first resistor having a first terminal and a second terminal, a second resistor having a third terminal and a fourth terminal, the third terminal coupled to the second terminal at a first node, a first transistor including a base terminal coupled to the fourth terminal of the second resistor at a second node, and a first current terminal coupled to the fourth terminal of the second resistor, a comparator including, a first input terminal coupled to the output terminal of the PTAT generation circuit at a third node, a second input terminal coupled to the second terminal and third terminal, and a third resistor having a fifth terminal coupled to the third terminal and the second input terminal at a fourth node.

Abstract: Methods, apparatus, and systems are disclosed for voltage supervisors. An example apparatus includes a first switch having a first source, a first drain, and a first gate, a first resistor having a first terminal and a second terminal, the first terminal coupled to the first source and second terminal coupled to the first drain, a second resistor having a third terminal and a fourth terminal, the third terminal coupled to the second terminal, a third resistor having a fifth terminal and a sixth terminal, the fifth terminal coupled to the fourth terminal, a fourth resistor having a seventh terminal and an eighth terminal, the seventh terminal coupled to the sixth terminal, a second switch having a second source, a second drain, and a second gate, the second source coupled to the seventh terminal, and a comparator having an output, the output coupled to the first gate and the second gate.

Abstract: A circuit includes a phase-locked loop having a phase-locked loop output to provide a first phase signal and a second phase signal phase delayed with respect to the first phase signal. The circuit further includes a digital circuit having a digital circuit input and an output. The digital circuit input couples to the phase-locked loop output. On the digital circuit output, the digital circuit is configured to provide a first digital-to-analog converter (DAC) enable signal and a second DAC enable signal. The circuit also includes first and second DACs. The first DAC is coupled to the digital circuit. The first DAC has a first enable input coupled to the digital circuit output to receive the first DAC enable signal. The second DAC is coupled to the digital circuit. The second DAC has a second enable input coupled to the digital circuit output to receive the second DAC enable signal.

Abstract: An electronic device has a DC/DC boost converter that includes a power NFET. The power NFET is coupled between a first pin, which can be coupled to a battery through an inductor, and a second pin that can be coupled to a ground plane. A switch-node is coupled to a third pin, which can be coupled to a diode to provide a boosted output voltage. A gate driver can receive a FET-on signal and drive a gate of the power NFET. A digital logic circuit provides the FET-on signal and includes an Ipeak gear-shifting circuit that dynamically changes the value of a peak inductor current responsive to one or more determinations that are related to one of the boosted output voltage and a switching frequency of the DC/DC boost converter.

Abstract: Methods, apparatus, and systems are disclosed for voltage supervisors. An example apparatus includes a first switch having a first source, a first drain, and a first gate, a first resistor having a first terminal and a second terminal, the first terminal coupled to the first source and second terminal coupled to the first drain, a second resistor having a third terminal and a fourth terminal, the third terminal coupled to the second terminal, a third resistor having a fifth terminal and a sixth terminal, the fifth terminal coupled to the fourth terminal, a fourth resistor having a seventh terminal and an eighth terminal, the seventh terminal coupled to the sixth terminal, a second switch having a second source, a second drain, and a second gate, the second source coupled to the seventh terminal, and a comparator having an output, the output coupled to the first gate and the second gate.

Abstract: A circuit includes a phase-locked loop having a phase-locked loop output to provide a first phase signal and a second phase signal phase delayed with respect to the first phase signal. The circuit further includes a digital circuit having a digital circuit input and an output. The digital circuit input couples to the phase-locked loop output. On the digital circuit output, the digital circuit is configured to provide a first digital-to-analog converter (DAC) enable signal and a second DAC enable signal. The circuit also includes first and second DACs. The first DAC is coupled to the digital circuit. The first DAC has a first enable input coupled to the digital circuit output to receive the first DAC enable signal. The second DAC is coupled to the digital circuit. The second DAC has a second enable input coupled to the digital circuit output to receive the second DAC enable signal.

Abstract: An electronic device has a DC/DC boost converter that includes a power NFET. The power NFET is coupled between a first pin, which can be coupled to a battery through an inductor, and a second pin that can be coupled to a ground plane. A switch-node is coupled to a third pin, which can be coupled to a diode to provide a boosted output voltage. A gate driver can receive a FET-on signal and drive a gate of the power NFET. A digital logic circuit provides the FET-on signal and includes an Ipeak gear-shifting circuit that dynamically changes the value of a peak inductor current responsive to one or more determinations that are related to one of the boosted output voltage and a switching frequency of the DC/DC boost converter.

Abstract: A voltage detector comprises an input, a resistor divider circuit having resistors coupled in series with one another between the input and a reference node, and N intermediate nodes joining adjacent pairs of the resistors. The voltage detector has N switches coupled to the respective intermediate nodes, as well as a comparator with an input coupled to the switches, a state machine having an input coupled to the output of the comparator, and a decoder having N decoder outputs coupled to respective control terminals of the N switches.