Abstract: Embodiments relate to an apparatus that includes: an input stage with an input Si slab height, an input Si waveguide height, and an input height difference between the input Si slab height and the input Si waveguide height; an output stage with an output Si slab height that is different from the input Si slab height, an output Si waveguide height that is different from the input Si waveguide height, and an output height difference between the output Si slab height and the output Si waveguide height that is different from the input height difference; and a transition stage positioned between the input stage and the output stage, wherein the transition stage has a transition Si slab height, a transition Si waveguide height, and a transition height difference between the transition Si slab height and the transition Si waveguide height. Other embodiments may be described and/or claimed.

Abstract: Embodiments herein relate to a chip comprising: a silicon substrate, a first waveguide that includes silicon and nitrogen, and a second waveguide that includes silicon. A portion of the first waveguide may overlap a portion of the second waveguide. An oxide layer may be coupled with a face of the silicon substrate. A first portion of the oxide layer between the silicon substrate and the first waveguide may have a thickness that is greater than a thickness of a second portion of the oxide layer that is between the second waveguide and the oxide layer. Other embodiments may be described and/or claimed.

Abstract: Embodiments herein may relate to an optical coupler that includes a silicon substrate and a silicon nitride waveguide positioned on the silicon substrate. The silicon nitride waveguide may be configured to guide an optical signal along a first axis. The optical coupler may further include a silicon waveguide positioned on the silicon substrate. The silicon waveguide may be configured to receive, from an output end of the silicon nitride waveguide, the optical signal at an input end of the silicon waveguide and guide the optical signal along a second axis that is at a first angle to the first axis. Other embodiments may be described and/or claimed.

Abstract: A photodetector structure over a partial length of a silicon waveguide structure within a photonic integrated circuit (PIC) chip. The photodetector structure is embedded within a cladding material surrounding the waveguide structure. The photodetector structure includes an absorption region, for example comprising Ge. A sidewall of the cladding material may be lined with a sacrificial spacer. After forming the absorption region, the sacrificial spacer may be removed and passivation material formed over a sidewall of the absorption region. Between the absorption region an impurity-doped portion of the waveguide structure there may be a carrier multiplication region, for example comprising crystalline silicon. If present, edge facets of the carrier multiplication region may be protected by a spacer material during the formation of an impurity-doped charge carrier layer. Occurrence of edge facets may be mitigated by embedding a portion of the photodetector structure with a thickness of the waveguide structure.

Abstract: Embedded three-dimensional electrode capacitors, and methods of fabricating three-dimensional electrode capacitors, are described. In an example, an integrated circuit structure includes a first metallization layer above a substrate, the first metallization layer having a first conductive structure in a first dielectric layer, the first conductive structure having a honeycomb pattern. An insulator structure is on the first conductive structure of the first metallization layer. A second metallization layer is above the first metallization layer, the second metallization layer having a second conductive structure in a second dielectric layer, the second conductive structure on the insulator structure, and the second conductive structure having the honeycomb pattern.