Abstract: A magnetoelectronic device structure 20 includes programming lines 26 and 28 and a magnetoelectronic device 24 between the programming lines 26 and 28. In one embodiment, layers 38, 40, and 42 of a colloidal dispersion of an electrically insulating material and magnetic particles are positioned between the magnetoelectronic device 24 and the programming lines 26 and 28. The magnetic particles cause the colloidal dispersion to have an enhanced magnetic permeability property. The layers 38, 40, and 42 are disposed by a spin coating technique.

Abstract: Structures for electrical communication with an overlying electrode for a semiconductor element and methods for fabricating such structures are provided. The structure for electrical communication with an overlying electrode comprises a first electrode having a lateral dimension, a semiconductor element overlying the first electrode, and a second electrode overlying the semiconductor element. The second electrode has a lateral dimension that is less than the lateral dimension of the first electrode. A conductive hardmask overlies the second electrode and is in electrical communication with the second electrode. The conductive hardmask has a lateral dimension that is substantially equal to the lateral dimension of the first electrode. A conductive contact element is in electrical communication with the conductive hardmask.

Abstract: A method for fabricating a cladded conductor (42) for use in a magnetoelectronics device is provided. The method includes providing a substrate (10) and forming a conductive barrier layer (12) overlying the substrate (10). A dielectric layer (16) is formed overlying the conductive barrier layer (12) and a conducting line (20) is formed within a portion of the dielectric layer (16). The dielectric layer (16) is removed and a flux concentrator (30) is formed overlying the conducting line (20).

Abstract: A method for fabricating a cladded conductor (42) for use in a magnetoelectronics device is provided. The method includes providing a substrate (10) and forming a conductive barrier layer (12) overlying the substrate (10). A dielectric layer (16) is formed overlying the conductive barrier layer (12) and a conducting line (20) is formed within a portion of the dielectric layer (16). The dielectric layer (16) is removed and a flux concentrator (30) is formed overlying the conducting line (20).

Abstract: A method of fabricating a magnetoresistive random access memory device comprising the steps of providing a substrate, forming a first conductive layer positioned on the substrate, forming a conductive material stack region with a flat surface, the conductive material stack region being positioned on a portion of the first conductive layer, and forming a magnetoresistive random access memory device positioned on the flat surface of the conductive material stack region, the magnetoresistive random access memory device being isolated from the first conductive layer and subsequent layers grown thereon.

Abstract: A method for fabricating a cladded conductor (42) for use in a magnetoelectronics device is provided. The method includes providing a substrate (10) and forming a conductive barrier layer (12) overlying the substrate (10). A dielectric layer (16) is formed overlying the conductive barrier layer (12) and a conducting line (20) is formed within a portion of the dielectric layer (16). The dielectric layer (16) is removed and a flux concentrator (30) is formed overlying the conducting line (20).

Abstract: A method of fabricating a magnetoresistive random access memory device comprising the steps of providing a substrate, forming a first conductive layer positioned on the substrate, forming a conductive material stack region with a flat surface, the conductive material stack region being positioned on a portion of the first conductive layer, and forming a magnetoresistive random access memory device positioned on the flat surface of the conductive material stack region, the magnetoresistive random access memory device being isolated from the first conductive layer and subsequent layers grown thereon.

Abstract: A method of fabricating a MRAM device with a taper comprising the steps of providing a substrate, forming a dielectric region with positioned on the substrate, patterning and isotropically etching through the dielectric region to the substrate to form a trench, depositing the MRAM device within the trench wherein the MRAM device includes a first ferromagnetic region with a width positioned on the substrate, a non-ferromagnetic spacer layer with a width positioned on the first ferromagnetic region, and a second ferromagnetic region with a width positioned on the non-ferromagnetic spacer layer wherein the taper is formed by making the width of the first ferromagnetic region greater than the width of the non-ferromagnetic spacer layer, and the width of the non-ferromagnetic spacer layer greater than the width of the second ferromagnetic region so that the first ferromagnetic region is separated from the second ferromagnetic region.

Abstract: A method of fabricating an MRAM cell includes providing an isolation transistor on a semiconductor substrate and forming an interconnect stack on the substrate in communication with one terminal of the transistor. A via is formed on the upper end of the stack so as to extend from a position below the digit line to a position above the digit line. The via also extends above the upper surface of a dielectric layer to provide an alignment key. A MTJ memory cell is positioned on the upper surface in contact with the via, and the ends of a free layer of magnetic material are spaced from the ends of a pinned edge of magnetic material by using sidewall spacers and selective etching.

Abstract: A process for improving uniformity across the surface of a substrate during a plasma process such as plasma etching. A conductive plane is formed at the back surface of the substrate. A plasma process is then performed to the front surface of the substrate. The conductive plane may then be removed upon completion of the plasma process and before final processing steps.

Abstract: An improved and novel MRAM device with magnetic memory elements and circuitry for controlling magnetic memory elements is provided. The circuitry, for example, transistor (12a) having a gate (17a), a drain (18) and a source (16a) is integrated on a substrate (11) and coupled to a magnetic memory element (43) on the circuitry through a plug conductor (19a) and a conductor line (45). The circuitry is fabricated first under the CMOS process and then magnetic memory elements (43, 44). Digit line (29) and bit line (48) are placed under and on top of magnetic memory element (43), respectively, and enabled to access magnetic memory element (43). These lines are enclosed by a high permeability layer (31, 56, 58) excluding a surface facing magnetic memory element (43), which shields and focuses a magnetic field toward magnetic memory element (43).

Abstract: An improved and novel fabrication method for magnetoresistive random access memory (MRAM) is provided. An MRAM device has memory elements and circuitry for managing the memory elements. The circuitry includes transistor (12a), digit line (29), etc., which are integrated on a substrate (11). The circuitry is fabricated first under the CMOS process and then magnetic memory elements (53, 54). A dielectric layer (40, 41) is deposited on the circuit, and trenches (42, 43) are formed in the dielectric layer. A blanket layer (46), which includes magnetic layers (48, 49) and a non-magnetic layer (50) sandwiched by the magnetic layers, is deposited on dielectric layer (41) and in the trenches. Then, the blanket layer outside the trenches is removed and MRAM elements (53, 54) are formed in the trenches.

Abstract: An improved and novel MRAM device with magnetic memory elements and circuitry for controlling magnetic memory elements is provided. The circuitry, for example, transistor (12a) having a gate (17a), a drain (18) and a source (16a) is integrated on a substrate (11) and coupled to a magnetic memory element (43) on the circuitry through a plug conductor (19a) and a conductor line (45). The circuitry is fabricated first under the CMOS process and then magnetic memory elements (43, 44). Digit line (29) and bit line (48) are placed under and on top of magnetic memory element (43), respectively, and enabled to access magnetic memory element (43). These lines are enclosed by a high permeability layer (31, 56, 58) excluding a surface facing magnetic memory element (43), which shields and focuses a magnetic field toward magnetic memory element (43).

Abstract: A manufacturable III-V semiconductor structure having small geometries is fabricated. A silicon nitride layer is formed on a III-V semiconductor material and a dielectric layer comprised of aluminum is formed on the silicon nitride layer. Another dielectric layer comprised of silicon and oxygen is formed over the dielectric layer comprised of aluminum. The dielectric layer comprised of aluminum acts as an etch stop for the etching of the dielectric layer comprised of silicon and oxygen with a high power reactive ion etch. The dielectric layer comprised of aluminum may then be etched with a wet etchant which does not substantially etch the silicon nitride layer. Damage to the surface of the semiconductor material by exposure to the high power reactive ion etch is prevented by forming the dielectric layer comprised of aluminum between the silicon nitride layer and the dielectric layer comprised of silicon and oxygen.