Abstract: Certain embodiments for reducing instruction storage space for a processor integrated in a network adapter chip may include generating MIPS instructions from corresponding new instructions. The new instructions may be in patch code instruction (PCI) format. The new instructions may be decoded and the MIPS instructions may be generated by a MIPS processor within a network adapter chip. Decoding the new instructions may also be referred to as interpreting the new instructions. The new instructions may comprise fewer bits than the generated MIPS instructions. The generated MIPS instructions may be executed by the MIPS processor within the network adapter chip.

Abstract: Certain embodiments for a self-booting Ethernet controller chip (NAC) may comprise a processor within the NAC that determines whether legacy boot code is present in memory external to the NAC. If legacy boot code is present in the external memory, the NAC may boot from the legacy boot code. If the legacy boot code is not present in the external memory, the processor may boot the NAC from the self-boot code in the ROM within the NAC. The processor may also read network configuration data from the external memory. The network configuration data may be stored, for example, in a NVRAM. The processor may copy the network configuration data from the NVRAM to a RAM within the NAC while booting.

Abstract: Certain embodiments for modifying operation of ROM based boot code may include modifying a bootup sequence for boot code resident in a ROM within a network adapter chip (NAC). The bootup sequence may be modified during booting of the NAC using code patches in memory external to the NAC. The boot code may comprise ROM loader code and/or self-boot code in the ROM within the NAC. Execution of the self-boot code may comprise execution of code patches. The code patches may comprise initialization code patches and service code patches. The code patches may be executed in place of functions in the self-boot code or in addition to the functions in the self-boot code. Additionally, the code patches may be configured such that a function in the self-boot code may be effectively deleted where no corresponding code patch may be executed in place of the function.

Abstract: Certain embodiments for modifying operation of ROM based boot code may include modifying a bootup sequence for boot code resident in a ROM within a network adapter chip (NAC). The bootup sequence may be modified during booting of the NAC using code patches in memory external to the NAC. The boot code may comprise ROM loader code and/or self-boot code in the ROM within the NAC. Execution of the self-boot code may comprise execution of code patches. The code patches may comprise initialization code patches and service code patches. The code patches may be executed in place of functions in the self-boot code or in addition to the functions in the self-boot code. Additionally, the code patches may be configured such that a function in the self-boot code may be effectively deleted where no corresponding code patch may be executed in place of the function.

Abstract: Certain embodiments for a self-booting Ethernet controller chip (NAC) may comprise a processor within the NAC that determines whether legacy boot code is present in memory external to the NAC. If legacy boot code is present in the external memory, the NAC may boot from the legacy boot code. If the legacy boot code is not present in the external memory, the processor may boot the NAC from the self-boot code in the ROM within the NAC. The processor may also read network configuration data from the external memory. The network configuration data may be stored, for example, in a NVRAM. The processor may copy the network configuration data from the NVRAM to a RAM within the NAC while booting.

Abstract: Certain embodiments for reducing instruction storage space for a processor integrated in a network adapter chip may include generating MIPS instructions from corresponding new instructions. The new instructions may be in patch code instruction (PCI) format. The new instructions may be decoded and the MIPS instructions may be generated by a MIPS processor within a network adapter chip. Decoding the new instructions may also be referred to as interpreting the new instructions. The new instructions may comprise fewer bits than the generated MIPS instructions. The generated MIPS instructions may be executed by the MIPS processor within the network adapter chip.