Patents by Inventor Kemal Aygun
Kemal Aygun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11983135Abstract: Embodiments herein relate to systems, apparatuses, or processes for improving off-package edge bandwidth by overlapping electrical and optical serialization/deserialization (SERDES) interfaces on an edge of the package. In other implementations, off-package bandwidth for a particular edge of a package may use both an optical fanout and an electrical fanout on the same edge of the package. In embodiments, the optical fanout may use a top surface or side edge of a die and the electrical fanout may use the bottom side edge of the die. Other embodiments may be described and/or claimed.Type: GrantFiled: September 25, 2020Date of Patent: May 14, 2024Assignee: Intel CorporationInventors: Dheeraj Subbareddy, Ankireddy Nalamalpu, Anshuman Thakur, Md Altaf Hossain, Mahesh Kumashikar, Kemal Aygün, Casey Thielen, Daniel Klowden, Sandeep B. Sane
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Publication number: 20240113049Abstract: Embodiments of a microelectronic assembly that includes: a package substrate, comprising buildup layers of an organic dielectric material and a plurality of layers of conductive traces in the organic dielectric material, the package substrate having a first surface and a second surface opposite the first surface; and a plurality of integrated circuit (IC) dies coupled to the package substrate on the first side. The plurality of layers of conductive traces comprises a pair of stripline traces or microstrips in one of the layers, the stripline traces or microstrips are surrounded by air gap structures in the organic dielectric material, and the air gap structures are exposed on the first surface.Type: ApplicationFiled: October 3, 2022Publication date: April 4, 2024Applicant: Intel CorporationInventors: Kristof Kuwawi Darmawikarta, Cemil S. Geyik, Kemal Aygun, Tarek A. Ibrahim, Wei-Lun Jen, Zhiguo Qian, Dilan Seneviratne
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Publication number: 20240105572Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (IC) assemblies. In some embodiments, an IC package assembly may include a first package substrate configured to route input/output (I/O) signals and ground between a die and a second package substrate. The first package substrate may include a plurality of contacts disposed on one side of the first package substrate and at least two ground vias of a same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with an individual contact. Other embodiments may be described and/or claimed.Type: ApplicationFiled: December 5, 2023Publication date: March 28, 2024Inventors: Zhiguo QIAN, Kemal AYGUN, Yu ZHANG
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Patent number: 11923308Abstract: Generally discussed herein are systems, devices, and methods to reduce crosstalk interference. An interconnect structure can include a first metal layer, a second metal layer, a third metal layer, the first metal layer closer to the first and second dies than the second and third metal layers, the first metal layer including a ground plane within a footprint of a bump field of the interconnect structure and signal traces outside the footprint of the bump field.Type: GrantFiled: December 8, 2020Date of Patent: March 5, 2024Assignee: Intel CorporationInventors: Zhiguo Qian, Kemal Aygun
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Publication number: 20240070366Abstract: A package substrate stack modeler includes a manufacturing modeler, configured to generate a model of a real package substrate stack based on an ideal design of the package substrate stack; a signal integrity model, configured to determine a signal integrity of a metal trace of the real package substrate stack; and a yield model, configured to determine a yield of the real package substrate stack; wherein the metal trace comprises a first value of a trace variable; further comprising a processor, configured to select a second value of the trace variable of the metal trace based on the determined signal integrity of the metal trace or the determined yield of the package substrate stack model.Type: ApplicationFiled: August 25, 2022Publication date: February 29, 2024Inventors: Nicholas HAEHN, Raquel DE SOUZA BORGES FERREIRA, Siddharth ALUR, Prakaram JOSHI, Dhanya ATHREYA, Yidnekachew MEKONNEN, Ali HARIRI, Andrea NICOLAS, Sri Chaitra Jyotsna CHAVALI, Kemal AYGUN
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Publication number: 20240063100Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first layer, where the first layer comprises glass, a second layer over the first layer, where the second layer comprises glass, and a third layer over the second layer, where the third layer comprises glass. In an embodiment, a pair of traces are in the second layer, and a first gap is below the pair of traces, where the first gap is in the first layer and the second layer. In an embodiment, a second gap is above the pair of traces, where the second gap is in the second layer and the third layer.Type: ApplicationFiled: August 16, 2022Publication date: February 22, 2024Inventors: Brandon C. MARIN, Mohammad Mamunur RAHMAN, Jeremy D. ECTON, Gang DUAN, Suddhasattwa NAD, Srinivas V. PIETAMBARAM, Kemal AYGÜN, Cemil GEYIK
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Patent number: 11903138Abstract: Fine feature formation techniques for printed circuit boards are described. In one embodiment, for example, a method may comprise fabricating a conductive structure on a low density interconnect (LDI) printed circuit board (PCB) according to an LDI fabrication process and forming one or more fine conductive features on the LDI PCB by performing a fine feature formation (FFF) process, the FFF process to comprise removing conductive material of the conductive structure along an excision path to form a fine gap region within the conductive structure. Other embodiments are described and claimed.Type: GrantFiled: July 22, 2021Date of Patent: February 13, 2024Assignee: Intel CorporationInventors: Eric Li, Kemal Aygun, Kai Xiao, Gong Ouyang, Zhichao Zhang
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Patent number: 11901280Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (IC) assemblies. In some embodiments, an IC package assembly may include a first package substrate configured to route input/output (I/O) signals and ground between a die and a second package substrate. The first package substrate may include a plurality of contacts disposed on one side of the first package substrate and at least two ground vias of a same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with an individual contact. Other embodiments may be described and/or claimed.Type: GrantFiled: September 29, 2022Date of Patent: February 13, 2024Assignee: Intel CorporationInventors: Zhiguo Qian, Kemal Aygun, Yu Zhang
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Patent number: 11887932Abstract: An apparatus is provided which comprises: a substrate, the substrate comprising crystalline material, a first set of one or more contacts on a first substrate surface, a second set of one or more contacts on a second substrate surface, the second substrate surface opposite the first substrate surface, a first via through the substrate coupled with a first one of the first set of contacts and with a first one of the second set of contacts; a second via through the substrate coupled with a second one of the first set of contacts and with a second one of the second set of contacts, a trench in the substrate from the first substrate surface toward the second substrate surface, wherein the trench is apart from, and between, the first via and the second via, and dielectric material filling the trench. Other embodiments are also disclosed and claimed.Type: GrantFiled: March 1, 2022Date of Patent: January 30, 2024Assignee: Intel CorporationInventors: Kemal Aygun, Zhiguo Qian, Jianyong Xie
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Publication number: 20240030143Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, an interconnect bridge embedded in the substrate, and at least one vertical interconnect structure disposed through a portion of the interconnect bridge, wherein the at least one vertical interconnect structure is electrically and physically coupled to the die.Type: ApplicationFiled: October 5, 2023Publication date: January 25, 2024Inventors: Kemal AYGUN, Zhiguo QIAN, Jianyong XIE
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Publication number: 20240006289Abstract: An electronic device includes a substrate including a core layer having a first surface and a second surface opposite the first surface, and at least one coaxial through-hole extending vertically through the core layer from the first surface to the second surface. The coaxial through-hole includes at least a first through-via that includes electrically conductive material extending through the core layer from the first surface to the second surface, and a conductive layer including the same or different electrically conductive material extending vertically through the core layer from the first surface to the second surface and surrounding the first through-via. The conductive layer is to be connected to a ground voltage and is electrically isolated from the first through-via.Type: ApplicationFiled: June 29, 2022Publication date: January 4, 2024Inventors: Kristof Darmawikarta, Kemal Aygun, Brandon C. Marin, Srinivas Venkata Ramanuja Pietambaram, Zhiguo Qian, Jiwei Sun
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Publication number: 20230420347Abstract: Embodiments of a microelectronic assembly comprise: a package substrate having a first face and an opposing second face, the package substrate comprising a conductive trace in a dielectric material, a conductive structure at least partially surrounding the conductive trace and separated from the conductive trace by the dielectric material; and an integrated circuit (IC) die attached to the first face of the package substrate and coupled to the conductive trace by a conductive pathway through the package substrate. The conductive trace has a non-rectangular cross-section with rounded corners, the conductive structure comprises a plurality of conductive planes parallel to the conductive trace and coupled to a ground connection.Type: ApplicationFiled: June 23, 2022Publication date: December 28, 2023Applicant: Intel CorporationInventors: Cemil Geyik, Zhiguo Qian, Kristof Kuwawi Darmawikarta, Zhichao Zhang, Kemal Aygun
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Publication number: 20230420358Abstract: Disclosed herein are silver-coated conductive structures in integrated circuit (IC) package supports, as well as related methods and devices. For example, in some embodiments, an IC package support may include a conductive line, a first material layer on a top surface and on side surfaces of the conductive line, the first material layer including silver, and a second material layer on the first material layer, the second material layer including silicon or aluminum, and one or more of nitrogen and oxygen.Type: ApplicationFiled: June 28, 2022Publication date: December 28, 2023Applicant: Intel CorporationInventors: Cemil S. Geyik, Kristof Kuwawi Darmawikarta, Zhiguo Qian, Kemal Aygun, Jung Kyu Han, Srinivas V. Pietambaram, Rengarajan Shanmugam, Robert L. Sankman
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Publication number: 20230420377Abstract: Embodiments of a microelectronic assembly comprise: a package substrate comprising a conductive trace in a dielectric material, the conductive trace surrounded by a conductive structure coupled to a ground connection, the package substrate further comprising metallization layers alternating with dielectric layers of the dielectric material; and an integrated circuit (IC) die coupled to a surface of the package substrate, the IC die being coupled to the conductive trace by a conductive pathway. The dielectric layers and the metallization layers are parallel to the surface of the package substrate, the conductive trace comprises a trench via in one of the dielectric layers, and the conductive structure comprises grounded plates extending across a length and width of the package substrate in metallization layers on either side of the dielectric layer.Type: ApplicationFiled: June 23, 2022Publication date: December 28, 2023Applicant: Intel CorporationInventors: Cemil Geyik, Kemal Aygun, Zhiguo Qian, Kristof Kuwawi Darmawikarta, Zhichao Zhang
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Patent number: 11837549Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, an interconnect bridge embedded in the substrate, and at least one vertical interconnect structure disposed through a portion of the interconnect bridge, wherein the at least one vertical interconnect structure is electrically and physically coupled to the die.Type: GrantFiled: December 27, 2022Date of Patent: December 5, 2023Assignee: Intel CorporationInventors: Kemal Aygun, Zhiguo Qian, Jianyong Xie
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Patent number: 11817391Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, an interconnect bridge embedded in the substrate, and at least one vertical interconnect structure disposed through a portion of the interconnect bridge, wherein the at least one vertical interconnect structure is electrically and physically coupled to the die.Type: GrantFiled: March 30, 2023Date of Patent: November 14, 2023Assignee: Intel CorporationInventors: Kemal Aygun, Zhiguo Qian, Jianyong Xie
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Patent number: 11810859Abstract: Structures are described that include multi-layered adhesion promotion films over a conductive structure in a microelectronic package. The multi-layered aspect provides adhesion to surrounding dielectric material without a roughened surface of the conductive structure. Furthermore, the multi-layered aspect allows for materials with different dielectric constants to be used, the average of which can provide a closer match to the dielectric constant of the surrounding dielectric material. According to an embodiment, a first dielectric layer that includes at least one nitride material can provide good adhesion with the underlying conductive structure, while one or more subsequent dielectric layers that include at least one oxide material can provide different dielectric constant values (e.g., typically lower) compared to the first dielectric layer to bring the overall dielectric constant closer to that of a surrounding dielectric material.Type: GrantFiled: February 18, 2020Date of Patent: November 7, 2023Assignee: Intel CorporationInventors: Srinivas V. Pietambaram, Rahul N. Manepalli, Cemil S. Geyik, Kemal Aygun
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Publication number: 20230352416Abstract: Methods, apparatus, systems, and articles of manufacture to improve signal integrity performance in integrated circuit packages are disclosed. An integrated circuit (IC) package includes a substrate; a first conductive pad in a first metal layer in the substrate; and a second conductive pad in a second metal layer in the substrate. The first metal layer is adjacent the second metal layer with no intervening metal layers therebetween. The integrated circuit (IC) package further includes a conductive protrusion extending from the first conductive pad toward the second conductive pad.Type: ApplicationFiled: April 29, 2022Publication date: November 2, 2023Inventors: Cemil Geyik, Kemal Aygun, Yidnekachew Mekonnen, Zhichao Zhang, Suddhasattwa Nad
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Publication number: 20230317588Abstract: Embodiments disclosed herein include electronic packages In an embodiment, the electronic package comprises first substrate layers, and a core under the first substrate layers. In an embodiment, second substrate layers are under the core, and an interconnect is through the first substrate layers, the core, and the second substrate layers. In an embodiment, a portion of the interconnect through the second substrate layers comprises a pad, and a plurality of vias extending away from the pad.Type: ApplicationFiled: March 29, 2022Publication date: October 5, 2023Inventors: Jiwei SUN, Zhiguo QIAN, Kemal AYGÜN
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Patent number: 11742275Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (IC) assemblies. In some embodiments, an IC package assembly may include a first package substrate configured to route input/output (I/O) signals and ground between a die and a second package substrate. The first package substrate may include a plurality of contacts disposed on one side of the first package substrate and at least two ground vias of a same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with an individual contact. Other embodiments may be described and/or claimed.Type: GrantFiled: December 30, 2021Date of Patent: August 29, 2023Assignee: Intel CorporationInventors: Zhiguo Qian, Kemal Aygun, Yu Zhang