Abstract: In some aspects, analyte test strip dispensers are provided. In some aspects, the analyte test strip dispensers store a plurality of analyte test strips and dispense one or more analyte test strips when needed. The analyte test strips may be stacked with an analyte test strip at one of the stack engaged with a dispensing element. The dispensing element may be slid relative to the dispenser to displace the analyte test strip out of the dispenser. In some aspects, an elastomeric cap having strong barrier properties for water vapor and moisture is provided. The elastomeric cap may be undersized in relation to the dispenser and stretched to couple to the dispenser, thus providing a pressure-fit seal along with strong barrier properties to water vapor and moisture.

Abstract: A system and method for protecting a circuit. The system includes a protection circuit that includes an inverter and a capacitor coupled to the inverter. The inverter and the capacitor are implemented using logic circuits of a circuit core, and the inverter shunts electrostatic discharge ESD current through the capacitor. According to the system and method disclosed herein, because the protection circuit shunt circuit shunts ESD current using logic circuits of the circuit core, ESD protection is achieved while not requiring large FETs. Also, the protection circuit protects circuits against ESD events that conventional FET cannot protect.

Abstract: A system and method for protecting a circuit. The system includes a protection circuit that includes an inverter and a capacitor coupled to the inverter. The inverter and the capacitor are implemented using logic circuits of a circuit core, and the inverter shunts electrostatic discharge ESD current through the capacitor. According to the system and method disclosed herein, because the protection circuit shunt circuit shunts ESD current using logic circuits of the circuit core, ESD protection is achieved while not requiring large FETs. Also, the protection circuit protects circuits against ESD events that conventional FET cannot protect.