Patents by Inventor Ken G. Pomaranski
Ken G. Pomaranski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8826288Abstract: A computer system provides for both lock-step and free-step processor modes, allowing for an effective tradeoff between performance and data integrity.Type: GrantFiled: April 19, 2005Date of Patent: September 2, 2014Assignee: Hewlett-Packard Development Company, L.P.Inventors: Andrew H. Barr, Ken G. Pomaranski
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Patent number: 8812781Abstract: A processor can write its state to an external state cache. Thus, in the event of a processor failure, the stored state can be read and assumed, either by the original processor or another processor. Thus, a process can be resumed from the stored state rather than reconstructed from initial conditions.Type: GrantFiled: April 19, 2005Date of Patent: August 19, 2014Assignee: Hewlett-Packard Development Company, L.P.Inventors: Ken G. Pomaranski, Andrew H. Barr, Dale J. Shidla
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Patent number: 8176250Abstract: A computer system comprising a processor, a memory, and a memory controller coupled to the processor and the memory is provided. The memory controller comprises a first cache and a cache control. The cache control is configured to cause a portion of the memory to be copied into the first cache. The cache control is configured to cause first information to be provided from the first cache to the processor in response to receiving a read transaction from the processor that includes an address in the portion of memory during testing of the portion.Type: GrantFiled: August 29, 2003Date of Patent: May 8, 2012Assignee: Hewlett-Packard Development Company, L.P.Inventors: Dale J. Shidla, Andrew H. Barr, Ken G. Pomaranski
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Patent number: 7797134Abstract: A computer system that includes a processor, a memory controller coupled to the processor, a memory coupled to the memory controller, a first input/output (I/O) controller coupled to the memory controller, a first expansion slot coupled to the first I/O controller, and a test module card coupled to the first expansion slot wherein the test module card is configured to cause tests to be performed on the memory using direct memory access (DMA) is provided.Type: GrantFiled: November 14, 2003Date of Patent: September 14, 2010Assignee: Hewlett-Packard Development Company, L.P.Inventors: Andrew H. Barr, Ken G. Pomaranski, Dale J. Shidla
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Patent number: 7487399Abstract: A computer system comprising a processor configured to cause an operating system to be booted, a test module, and a component coupled to the test module and configured to receive a clock input is provided. The test module is configured to cause the clock input to be provided to the component at a first frequency, and the test module is configured to cause a first test to be performed on the component subsequent to the clock input being provided to the component at the first frequency and the operating system being booted.Type: GrantFiled: November 7, 2003Date of Patent: February 3, 2009Assignee: Hewlett-Packard Development Company, L.P.Inventors: Ken G. Pomaranski, Andrew H. Barr, Dale J. Shidla
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Patent number: 7418367Abstract: A computer system including a system module, a test module, a first cell, and a second cell is provided. The system module is configured to cause the test module to test the first cell subsequent to the second cell being allocated to a first instance of an operating system.Type: GrantFiled: October 31, 2003Date of Patent: August 26, 2008Assignee: Hewlett-Packard Development Company, L.P.Inventors: Ken G. Pomaranski, Andrew H. Barr, Dale J. Shidla
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Patent number: 7350109Abstract: A computer system that includes a processor, a first bus coupled to the processor, a memory controller coupled to the first bus, a memory coupled to the memory controller, a first input/output (I/O) controller coupled to the first bus, and a test module coupled to the first I/O controller is provided. The test module is configured to cause tests to be performed on the memory using the first bus.Type: GrantFiled: November 14, 2003Date of Patent: March 25, 2008Assignee: Hewlett-Packard Development Company, L.P.Inventors: Andrew H. Barr, Ken G. Pomaranski, Dale J. Shidla
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Patent number: 7072788Abstract: A computer system comprising an operating system, a first component that comprises a first test module, a second component that comprises a second test module, and an interconnect coupling the first component and the second component is provided. The first test module is configured to provide a first test pattern to the second test module on the interconnect in response to a first signal from the operating system.Type: GrantFiled: December 4, 2003Date of Patent: July 4, 2006Assignee: Hewlett-Packard Development CompanyInventors: Ken G. Pomaranski, Andrew H. Barr, Dale J. Shidla
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Patent number: 6995581Abstract: A method and corresponding apparatus for detecting and rejecting high impedance failures in chip interconnects use monitoring circuitry on a chip to provide accurate and pro-active prediction of interconnect failures. The apparatus may include a resistance continuity monitoring circuit (RCMC), and a signal path connecting a representative set of pins to the RCMC. The RCMC measures the resistance of a connection of the representative set of pins with a circuit board during system operation and outputs a measured resistance data. The apparatus further includes additional analog-to-digital (A/D) hardware to perform an analog to digital conversion of the measured resistance data. Additional on-chip circuitry and/or microcode may be used to perform an algorithm on the digital resistance data to generate an interconnect status signal. For example, the method may output a failure signal when the measured resistance data exceeds a threshold resistance value.Type: GrantFiled: January 13, 2005Date of Patent: February 7, 2006Assignee: Hewlett-Packard Development Company, L.P.Inventors: Andrew H. Barr, Ken G. Pomaranski, Dale J. Shidla
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Patent number: 6985826Abstract: A computer system comprising a first processor that is configured to cause an operating system to be booted, a test module, a component coupled to the test module, and a power supply coupled to the test module and the component is provided. The test module is configured to provide a first signal to the power supply to cause a first voltage to be provided to the component, and the test module is configured to cause a first test to be performed on the component subsequent to the first voltage being provided to the component and the operating system being booted.Type: GrantFiled: October 31, 2003Date of Patent: January 10, 2006Assignee: Hewlett-Packard Development Company, L.P.Inventors: Ken G. Pomaranski, Andrew H. Barr, Dale J. Shidla
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Patent number: 6940288Abstract: An apparatus and a method for detecting high impedance failures in system interconnects. The apparatus and method may measure resistance of a connection of one or more representative sets of pins on a partitioned chip to a circuit board and determine if the measured resistance of each of the one or more representative sets of pins is less than a threshold value. The measuring step is executed while the circuit board is operating.Type: GrantFiled: June 4, 2003Date of Patent: September 6, 2005Assignee: Hewlett-Packard Development Company, L.P.Inventors: Andrew H. Barr, Ken G. Pomaranski, Dale J. Shidla
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Patent number: 6895353Abstract: A method and corresponding apparatus for monitoring high impedance failures in chip interconnects use monitoring circuitry on a chip to provide accurate and pro-active prediction of interconnect failures. The apparatus may include a resistance continuity monitoring circuit (RCMC), and a signal path connecting a representative set of pins to the RCMC. The RCMC measures the resistance of a connection of the representative set of pins with a circuit board during system operation and outputs a measured resistance data. The apparatus further includes additional analog-to-digital (A/D) hardware to perform an analog to digital conversion of the measured resistance data. The apparatus further includes a system interface for connecting the monitoring circuitry with other system management devices. The method then performs an algorithm on the measured resistance data, potentially warning of likely interconnect failures.Type: GrantFiled: June 4, 2003Date of Patent: May 17, 2005Assignee: Hewlett-Packard Development Company, L.P.Inventors: Andrew H. Barr, Ken G. Pomaranski, Dale J. Shidla
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Patent number: 6879173Abstract: A method and corresponding apparatus for detecting and rejecting high impedance failures in chip interconnects use monitoring circuitry on a chip to provide accurate and pro-active prediction of interconnect failures. The apparatus may include a resistance continuity monitoring circuit (RCMC), and a signal path connecting a representative set of pins to the RCMC. The RCMC measures the resistance of a connection of the representative set of pins with a circuit board during system operation and outputs a measured resistance data. The apparatus further includes additional analog-to-digital (A/D) hardware to perform an analog to digital conversion of the measured resistance data. Additional on-chip circuitry and/or microcode may be used to perform an algorithm on the digital resistance data to generate an interconnect status signal. For example, the method may output a failure signal when the measured resistance data exceeds a threshold resistance value.Type: GrantFiled: June 4, 2003Date of Patent: April 12, 2005Assignee: Hewlett-Packard Development Company, L.P.Inventors: Andrew H. Barr, Ken G. Pomaranski, Dale J. Shidla
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Publication number: 20040245996Abstract: An apparatus and a method for detecting high impedance failures in system interconnects. The apparatus and method may measure resistance of a connection of one or more representative sets of pins on a partitioned chip to a circuit board and determine if the measured resistance of each of the one or more representative sets of pins is less than a threshold value. The measuring step is executed while the circuit board is operating.Type: ApplicationFiled: June 4, 2003Publication date: December 9, 2004Inventors: Andrew H. Barr, Ken G. Pomaranski, Dale J. Shidla
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Publication number: 20040245981Abstract: A method and corresponding apparatus for detecting and rejecting high impedance failures in chip interconnects use monitoring circuitry on a chip to provide accurate and pro-active prediction of interconnect failures. The apparatus may include a resistance continuity monitoring circuit (RCMC), and a signal path connecting a representative set of pins to the RCMC. The RCMC measures the resistance of a connection of the representative set of pins with a circuit board during system operation and outputs a measured resistance data. The apparatus further includes additional analog-to-digital (A/D) hardware to perform an analog to digital conversion of the measured resistance data. Additional on-chip circuitry and/or microcode may be used to perform an algorithm on the digital resistance data to generate an interconnect status signal. For example, the method may output a failure signal when the measured resistance data exceeds a threshold resistance value.Type: ApplicationFiled: June 4, 2003Publication date: December 9, 2004Inventors: Andrew H. Barr, Ken G. Pomaranski, Dale J. Shidla
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Publication number: 20040246008Abstract: An apparatus and a method for detecting high impedance failures in system interconnects. The apparatus and method may measure resistance of a connection of a representative set of pins on a partitioned chip to a circuit board and determine if the measured resistance is within a certain percentage of a good resistance value. The measuring step is executed while the circuit board is operating.Type: ApplicationFiled: June 4, 2003Publication date: December 9, 2004Inventors: Andrew H. Barr, Ken G. Pomaranski, Dale J. Shidla
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Publication number: 20040249612Abstract: A method and corresponding apparatus for monitoring high impedance failures in chip interconnects use monitoring circuitry on a chip to provide accurate and pro-active prediction of interconnect failures. The apparatus may include a resistance continuity monitoring circuit (RCMC), and a signal path connecting a representative set of pins to the RCMC. The RCMC measures the resistance of a connection of the representative set of pins with a circuit board during system operation and outputs a measured resistance data. The apparatus further includes additional analog-to-digital (A/D) hardware to perform an analog to digital conversion of the measured resistance data. The apparatus further includes a system interface for connecting the monitoring circuitry with other system management devices. The method then performs an algorithm on the measured resistance data, potentially warning of likely interconnect failures.Type: ApplicationFiled: June 4, 2003Publication date: December 9, 2004Inventors: Andrew H. Barr, Ken G. Pomaranski, Dale J. Shidla
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Publication number: 20040249585Abstract: An apparatus and a method for detecting high impedance failures in system interconnects. The apparatus may include a resistance continuity monitoring circuit (RCMC), a signal path connecting a representative set of pins to the RCMC, and a communications link for connecting the RCMC with other system components. The RCMC measures the resistance of a connection of the representative set of pins on a chip with a circuit board and outputs measured resistance data. The apparatus and method may partition a chip into pin areas, select a representative set of pins in a pin area, measure resistance of the connection of the representative set of pins to the circuit board, and perform an algorithm on the measured resistance data. The pin area includes pins connecting the chip to a circuit board.Type: ApplicationFiled: June 4, 2003Publication date: December 9, 2004Inventors: Andrew H. Barr, Ken G. Pomaranski, Dale J. Shidla