Patents by Inventor Ken-Ichi Nonaka
Ken-Ichi Nonaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8664909Abstract: A miniaturizable, low-cost highly reliable inverter unit. A control circuit section for controlling operating timing of high breakdown voltage semiconductor elements included in an inverter circuit section and first and second drive and abnormality detection circuit sections for outputting drive signals for driving the high breakdown voltage semiconductor elements according to the operating timing and for feeding back an abnormality of the inverter circuit section to the control circuit section are formed on an SOI substrate as one integrated circuit chip. On the integrated circuit chip, circuit formation areas which differ in reference potential are separated from one another by dielectrics. A plurality of level shifters for transmitting signals exchanged between circuit formation areas separated by the dielectrics are formed.Type: GrantFiled: December 28, 2012Date of Patent: March 4, 2014Assignees: Fuji Electric Co., Ltd., Honda Motor Co., Ltd., Sharp Kabushiki-KaishaInventors: Hitoshi Sumida, Akinobu Teramoto, Ken-ichi Nonaka, Toshio Naka
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Patent number: 8653627Abstract: A semiconductor crystal having a recombination-inhibiting semiconductor layer of a second conductive type that is disposed in the vicinity of the surface between a base contact region and emitter regions and that separates the semiconductor surface having a large number of surface states from the portion that primarily conducts the positive hole electric current and the electron current. Recombination is inhibited, and the current amplification factor is thereby improved and the ON voltage reduced.Type: GrantFiled: May 6, 2013Date of Patent: February 18, 2014Assignee: Honda Motor Co., Ltd.Inventor: Ken-ichi Nonaka
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Publication number: 20130240910Abstract: A semiconductor crystal having a recombination-inhibiting semiconductor layer of a second conductive type that is disposed in the vicinity of the surface between a base contact region and emitter regions and that separates the semiconductor surface having a large number of surface states from the portion that primarily conducts the positive hole electric current and the electron current. Recombination is inhibited, and the current amplification factor is thereby improved and the ON voltage reduced.Type: ApplicationFiled: May 6, 2013Publication date: September 19, 2013Applicant: HONDA MOTOR CO.,LTD.Inventor: Ken-ichi NONAKA
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Patent number: 8460994Abstract: A semiconductor crystal includes a recombination-inhibiting semiconductor layer (17) of a second conductive type that is disposed in the vicinity of the surface between a base contact region (16) and emitter regions (14) and that separates the semiconductor surface having a large number of surface states from the portion that primarily conducts the positive hole electric current and the electron current. Recombination is inhibited, and the current amplification factor is thereby improved and the ON voltage reduced.Type: GrantFiled: June 9, 2006Date of Patent: June 11, 2013Assignee: Honda Motor Co., Ltd.Inventor: Ken-ichi Nonaka
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Patent number: 8405343Abstract: A miniaturizable, low-cost highly reliable inverter unit. A control circuit section for controlling operating timing of high breakdown voltage semiconductor elements included in an inverter circuit section and first and second drive and abnormality detection circuit sections for outputting drive signals for driving the high breakdown voltage semiconductor elements according to the operating timing and for feeding back an abnormality of the inverter circuit section to the control circuit section are formed on an SOI substrate as one integrated circuit chip. On the integrated circuit chip, circuit formation areas which differ in reference potential are separated from one another by dielectrics. A plurality of level shifters for transmitting signals exchanged between circuit formation areas separated by the dielectrics are formed.Type: GrantFiled: May 19, 2011Date of Patent: March 26, 2013Assignees: Fuji Electric Systems Co., Ltd., Honda Motor Co., Ltd., Sharp Kabushiki-KaishaInventors: Hitoshi Sumida, Akinobu Teramoto, Ken-ichi Nonaka, Toshio Naka
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Patent number: 8105927Abstract: A method for manufacturing an ion implantation mask is disclosed which includes the steps of: forming an oxide film as a protective film over the entire surface of a semiconductor substrate; forming a thin metal film over the oxide film; and forming an ion-inhibiting layer composed of an ion-inhibiting metal over the thin metal film. The obtained ion implantation mask is used to form a deeper selectively electroconductive region.Type: GrantFiled: March 3, 2010Date of Patent: January 31, 2012Assignees: Honda Motor Co., Ltd., Shindengen Electric Manufacturing Co., Ltd.Inventors: Ken-ichi Nonaka, Hideki Hashimoto, Seiichi Yokoyama, Hiroaki Iwakuro, Koichi Nishikawa, Masaaki Shimizu, Yusuke Fukuda
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Publication number: 20110222257Abstract: A miniaturizable, low-cost highly reliable inverter unit. A control circuit section for controlling operating timing of high breakdown voltage semiconductor elements included in an inverter circuit section and first and second drive and abnormality detection circuit sections for outputting drive signals for driving the high breakdown voltage semiconductor elements according to the operating timing and for feeding back an abnormality of the inverter circuit section to the control circuit section are formed on an SOI substrate as one integrated circuit chip. On the integrated circuit chip, circuit formation areas which differ in reference potential are separated from one another by dielectrics. A plurality of level shifters for transmitting signals exchanged between circuit formation areas separated by the dielectrics are formed.Type: ApplicationFiled: May 19, 2011Publication date: September 15, 2011Inventors: Hitoshi SUMIDA, Akinobu Teramoto, Ken-ichi Nonaka, Toshio Naka
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Patent number: 7960937Abstract: A miniaturizable, low-cost highly reliable inverter unit. A control circuit section for controlling operating timing of high breakdown voltage semiconductor elements included in an inverter circuit section and first and second drive and abnormality detection circuit sections for outputting drive signals for driving the high breakdown voltage semiconductor elements according to the operating timing and for feeding back an abnormality of the inverter circuit section to the control circuit section are formed on an SOI substrate as one integrated circuit chip. On the integrated circuit chip, circuit formation areas which differ in reference potential are separated from one another by dielectrics. A plurality of level shifters for transmitting signals exchanged between circuit formation areas separated by the dielectrics are formed.Type: GrantFiled: September 7, 2005Date of Patent: June 14, 2011Assignees: Fuji Electric Systems Co., Ltd., Sharp Kabushiki Kaisha, Honda Motor Co., Ltd.Inventors: Hitoshi Sumida, Akinobu Teramoto, Ken-ichi Nonaka, Toshio Naka
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Patent number: 7867836Abstract: A method for manufacturing a junction semiconductor device having a drain region including a low-resistance layer of a first conductive type formed on one surface of a semiconductor crystal, a source region including a low-resistance layer of a first conductive type formed on the other surface of the semiconductor crystal, a gate region of a second conductive type formed on the periphery of the source region, a high-resistance layer of a first conductive type between the source region and the drain region, and a recombination-inhibiting semiconductor layer of a second conductive type provided in the vicinity of the surface of the semiconductor crystal between the gate region and the source region.Type: GrantFiled: September 3, 2008Date of Patent: January 11, 2011Assignee: Honda Motor Co., Ltd.Inventors: Ken-ichi Nonaka, Hideki Hashimoto, Seiichi Yokoyama, Kensuke Iwanaga, Yoshimitsu Saito
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Publication number: 20100159653Abstract: A method for manufacturing an ion implantation mask is disclosed which includes the steps of: forming an oxide film as a protective film over the entire surface of a semiconductor substrate; forming a thin metal film over the oxide film; and forming an ion-inhibiting layer composed of an ion-inhibiting metal over the thin metal film. The obtained ion implantation mask is used to form a deeper selectively electroconductive region.Type: ApplicationFiled: March 3, 2010Publication date: June 24, 2010Inventors: Ken-ichi NONAKA, Hideki HASHIMOTO, Seiichi YOKOYAMA, Hiroaki IWAKURO, Koichi NISHIKAWA, Masaaki SHIMIZU, Yusuke FUKUDA
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Patent number: 7709862Abstract: A method for manufacturing an ion implantation mask is disclosed which includes the steps of: forming an oxide film as a protective film over the entire surface of a semiconductor substrate; forming a thin metal film over the oxide film; and forming an ion-inhibiting layer composed of an ion-inhibiting metal over the thin metal film. The obtained ion implantation mask is used to form a deeper selectively electroconductive region.Type: GrantFiled: August 1, 2006Date of Patent: May 4, 2010Assignees: Honda Motor Co., Ltd., Shindengen Electric Manufacturing Co., Ltd.Inventors: Ken-ichi Nonaka, Hideki Hashimoto, Seiichi Yokoyama, Hiroaki Iwakuro, Koichi Nishikawa, Masaaki Shimizu, Yusuke Fukuda
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Publication number: 20100001290Abstract: A semiconductor crystal includes a recombination-inhibiting semiconductor layer (17) of a second conductive type that is disposed in the vicinity of the surface between a base contact region (16) and emitter regions (14) and that separates the semiconductor surface having a large number of surface states from the portion that primarily conducts the positive hole electric current and the electron current. Recombination is inhibited, and the current amplification factor is thereby improved and the ON voltage reduced.Type: ApplicationFiled: June 9, 2006Publication date: January 7, 2010Applicant: HONDA MOTOR CO., LTD.Inventor: Ken-ichi Nonaka
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Patent number: 7544552Abstract: A method for manufacturing a junction semiconductor device, having a step for forming a first high-resistance layer, a step for forming a channel-doped layer, a step for forming a second high-resistance layer, a step for forming a low-resistance layer of a first conductive type that acts as a source region, a step for performing partial etching to a midway depth of the second high-resistance layer and the low-resistance layer, a step for forming a gate region below the portion etched in the etching step, and a step for forming a protective film on the surface of the region between the gate region and the source region. A gate region is formed using relatively low energy ion implantation in the surface that has been etched in advance to a height that is between the lower surface of the source area and the upper surface of the channel-doped layer.Type: GrantFiled: March 23, 2006Date of Patent: June 9, 2009Assignees: Honda Motor Co., Ltd., Shindengen Electric Manufacturing Co., Ltd.Inventors: Ken-ichi Nonaka, Hideki Hashimoto, Seiichi Yokoyama, Kensuke Iwanaga, Yoshimitsu Saito, Hiroaki Iwakuro, Masaaki Shimizu, Yusuke Fukuda, Koichi Nishikawa, Yusuke Maeyama
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Publication number: 20090004790Abstract: A method for manufacturing a junction semiconductor device having a drain region including a low-resistance layer of a first conductive type formed on one surface of a semiconductor crystal, a source region including a low-resistance layer of a first conductive type formed on the other surface of the semiconductor crystal, a gate region of a second conductive type formed on the periphery of the source region, a high-resistance layer of a first conductive type between the source region and the drain region, and a recombination-inhibiting semiconductor layer of a second conductive type provided in the vicinity of the surface of the semiconductor crystal between the gate region and the source region.Type: ApplicationFiled: September 3, 2008Publication date: January 1, 2009Inventors: Ken-ichi NONAKA, Hideki Hashimoto, Seiichi Yokoyama, Kensuke Iwanaga, Yoshimitsu Saito
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Patent number: 7449734Abstract: A junction semiconductor device having a drain region including a low-resistance layer of a first conductive type formed on one surface of a semiconductor crystal, a source region including a low-resistance layer of a first conductive type formed on the other surface of the semiconductor crystal, a gate region of a second conductive type formed on the periphery of the source region, a high-resistance layer of a first conductive type between the source region and the drain region, and a recombination-inhibiting semiconductor layer of a second conductive type provided in the vicinity of the surface of the semiconductor crystal between the gate region and the source region.Type: GrantFiled: March 23, 2006Date of Patent: November 11, 2008Assignee: Honda Motor Co., Ltd.Inventors: Ken-ichi Nonaka, Hideki Hashimoto, Seiichi Yokoyama, Kensuke Iwanaga, Yoshimitsu Saito
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Publication number: 20070032002Abstract: A method for manufacturing an ion implantation mask is disclosed which includes the steps of: forming an oxide film as a protective film over the entire surface of a semiconductor substrate; forming a thin metal film over the oxide film; and forming an ion-inhibiting layer composed of an ion-inhibiting metal over the thin metal film. The obtained ion implantation mask is used to form a deeper selectively electroconductive region.Type: ApplicationFiled: August 1, 2006Publication date: February 8, 2007Applicants: HONDA MOTOR CO., LTD., Shindengen Electric Manufacturing Co., Ltd.Inventors: Ken-ichi Nonaka, Hideki Hashimoto, Seiichi Yokoyama, Hiroaki Iwakuro, Koichi Nishikawa, Masaaki Shimizu, Yusuke Fukuda
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Publication number: 20060216879Abstract: A method for manufacturing a junction semiconductor device, having a step for forming a first high-resistance layer, a step for forming a channel-doped layer, a step for forming a second high-resistance layer, a step for forming a low-resistance layer of a first conductive type that acts as a source region, a step for performing partial etching to a midway depth of the second high-resistance layer and the low-resistance layer, a step for forming a gate region below the portion etched in the etching step, and a step for forming a protective film on the surface of the region between the gate region and the source region. A gate region is formed using relatively low energy ion implantation in the surface that has been etched in advance to a height that is between the lower surface of the source area and the upper surface of the channel-doped layer.Type: ApplicationFiled: March 23, 2006Publication date: September 28, 2006Inventors: Ken-ichi Nonaka, Hideki Hashimoto, Seiichi Yokoyama, Kensuke Iwanaga, Yoshimitsu Saito, Hiroaki Iwakuro, Masaaki Shimizu, Yusuke Fukuda, Koichi Nishikawa, Yusuke Maeyama
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Publication number: 20060214200Abstract: A junction semiconductor device having a drain region comprising a low-resistance layer of a first conductive type formed on one surface of a semiconductor crystal, a source region comprising a low-resistance layer of a first conductive type formed on the other surface of the semiconductor crystal, a gate region of a second conductive type formed on the periphery of the source region, a high-resistance layer of a first conductive type between the source region and the drain region, and a recombination-inhibiting semiconductor layer of a second conductive type provided in the vicinity of the surface of the semiconductor crystal between the gate region and the source region.Type: ApplicationFiled: March 23, 2006Publication date: September 28, 2006Inventors: Ken-ichi Nonaka, Hideki Hashimoto, Seiichi Yokoyama, Kensuke Iwanaga, Yoshimitsu Saito
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Publication number: 20060050455Abstract: A miniaturizable, low-cost highly reliable inverter unit. A control circuit section for controlling operating timing of high breakdown voltage semiconductor elements included in an inverter circuit section and first and second drive and abnormality detection circuit sections for outputting drive signals for driving the high breakdown voltage semiconductor elements according to the operating timing and for feeding back an abnormality of the inverter circuit section to the control circuit section are formed on an SOI substrate as one integrated circuit chip. On the integrated circuit chip, circuit formation areas which differ in reference potential are separated from one another by dielectrics. A plurality of level shifters for transmitting signals exchanged between circuit formation areas separated by the dielectrics are formed.Type: ApplicationFiled: September 7, 2005Publication date: March 9, 2006Applicants: Fuji Electric Device Technology Co., Ltd., Sharp Kabushiki Kaisha, Honda Motor Co., Ltd.Inventors: Hitoshi Sumida, Akinobu Teramoto, Ken-ichi Nonaka, Toshio Naka
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Patent number: 6218667Abstract: A sensor element includes a light detecting section (2), a wiring section and a microlens section (7, 8). The light detecting section (2) is formed to be spaced from a substrate (1) to detect an incident light. The wiring section is composed of leg sections (3, 4) and outputting sections (11, 12) formed to be spaced from the substrate in a peripheral portion of the light detecting section. The wiring section connects the detecting result of the light detecting section to patterns on the substrate. The microlens section is formed to be spaced from the light detecting section to collect and output the incident light to the light detecting section. An area of the light detecting section is equal to or smaller than ¼ of an area of the sensor element. The sensor element may further include a reflecting film formed under the light detecting section to reflect the incident light which passes through the light detecting section.Type: GrantFiled: September 9, 1998Date of Patent: April 17, 2001Assignee: Honda Giken Kogyo Kabushiki KaishaInventors: Ken-Ichi Nonaka, Seiichi Yokoyama, Toshifumi Suzuki