Patents by Inventor Ken Marr
Ken Marr has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6353521Abstract: An integrated circuit having a voltage protection circuit in electrical communication with an input buffer of the integrated circuit and a method for providing voltage protection to the input buffer. In one exemplary embodiment, the voltage protection circuit is an active device, such as a transistor, in electrical communication with an input node of the input buffer. When the active device actuates it provides a current path which limits a potential seen at the input buffer to a value less than an electrostatic discharge (ESD) potential. In one implementation the active device responds to a voltage which develops in response to current flow in an ESD circuit, and in a further implementation it responds to a gate to source potential during an ESD event. In both implementations the active device is actuated during an ESD event and is deactuated during normal operation of the circuit.Type: GrantFiled: August 30, 2000Date of Patent: March 5, 2002Assignee: Micron Technology, Inc.Inventors: Dean Gans, Ken Marr
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Patent number: 6172899Abstract: A 4-T SRAM cell includes access transistors of a first type and cell (pull-up or pull-down) transistors of a second type. For example, the cell includes PMOS access transistors and NMOS pull-down transistors. The cell may also include leaky-junction or Schottky loads.Type: GrantFiled: May 8, 1998Date of Patent: January 9, 2001Assignee: Micron Technology. Inc.Inventors: Ken Marr, H. Montgomery Manning
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Patent number: 6163476Abstract: A 4-T SRAM cell includes access transistors of a first type and cell (pull-up or pull-down) transistors of a second type. For example, the cell includes PMOS access transistors and NMOS pull-down transistors. The cell may also include leaky-junction or Schottky loads.Type: GrantFiled: August 24, 1999Date of Patent: December 19, 2000Assignee: Micron Technology, Inc.Inventors: Ken Marr, H. Montgomery Manning
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Patent number: 6130811Abstract: An integrated circuit having a voltage protection circuit in electrical communication with an input buffer of the integrated circuit and a method for providing voltage protection to the input buffer are disposed. In one exemplary embodiment, the voltage protection circuit is an active device, such as a transistor, in electrical communication with an input node of the input buffer. When the active device actuates it provides a current path which limits a potential seen at the input buffer to a value less than an electrostatic discharge (ESD) potential. In one implementation the active device responds to a voltage which develops in response to current flow in an ESD circuit, and in a further implementation it responds to a gate to source potential during an ESD event. In both implementations the active device is actuated during an ESD event and is deactuated during normal operation of the circuit.Type: GrantFiled: January 7, 1997Date of Patent: October 10, 2000Assignee: Micron Technology, Inc.Inventors: Dean Gans, Ken Marr
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Patent number: 6117721Abstract: A semiconductor processing method of forming a static random access memory cell having an n-channel access transistor includes, providing a bulk semiconductor substrate; patterning the substrate for definition of field oxide regions and active area regions for the n-channel access transistor; subjecting the patterned substrate to oxidizing conditions to form a pair of field oxide regions and an intervening n-channel access transistor active area therebetween, the field oxide regions having respective bird's beak regions extending into the n-channel access transistor active area, the n-channel access transistor active area defining a central region away from the bird's beak regions; and conducting a p-type V.sub.T ion implant into the n-channel active area using the field oxide bird's beak regions as an implant mask to concentrate the V.sub.T implant in the central region of the active area.Type: GrantFiled: November 26, 1997Date of Patent: September 12, 2000Assignee: Micron Technology, Inc.Inventors: Charles H. Dennison, Ken Marr
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Patent number: 6044011Abstract: A 4-T SRAM cell includes access transistors of a first type and cell (pull-up or pull-down) transistors of a second type. For example, the cell includes PMOS access transistors and NMOS pull-down transistors. The cell may also include leaky-junction or Schottky loads.Type: GrantFiled: August 24, 1999Date of Patent: March 28, 2000Assignee: Micron Technology, Inc.Inventors: Ken Marr, H. Montgomery Manning
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Patent number: 5929495Abstract: A semiconductor processing method of forming a static random access memory cell having an n-channel access transistor includes, providing a bulk semiconductor substrate; patterning the substrate for definition of field oxide regions and active area regions for the n-channel access transistor; subjecting the patterned substrate to oxidizing conditions to form a pair of field oxide regions and an intervening n-channel access transistor active area therebetween, the field oxide regions having respective bird's beak regions extending into the n-channel access transistor active area, the n-channel access transistor active area defining a central region away from the bird's beak regions; and conducting a p-type V.sub.T ion implant into the n-channel active area using the field oxide bird's beak regions as an implant mask to concentrate the V.sub.T implant in the central region of the active area.Type: GrantFiled: February 24, 1998Date of Patent: July 27, 1999Assignee: Micron Technology, Inc.Inventors: Charles H. Dennison, Ken Marr
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Patent number: 5751046Abstract: A semiconductor processing method of forming a static random access memory cell having an n-channel access transistor includes providing a bulk semiconductor substrate; patterning the substrate for definition of field oxide regions and active area regions for the n-channel access transistor; subjecting the patterned substrate to oxidizing conditions to form a pair of field oxide regions and an intervening n-channel access transistor active area therebetween, the field oxide regions having respective bird's beak regions extending into the n-channel access transistor active area, the n-channel access transistor active area defining a central region away from the bird's beak regions; and conducting a p-type V.sub.T ion implant into the n-channel active area using the field oxide bird's beak regions as an implant mask to concentrate the V.sub.T implant in the central region of the active area.Type: GrantFiled: May 5, 1997Date of Patent: May 12, 1998Assignee: Micron Technology, Inc.Inventors: Charles H. Dennison, Ken Marr
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Patent number: 5739056Abstract: A semiconductor processing method of forming a static random access memory cell having an n-channel access transistor includes, providing a bulk semiconductor substrate; patterning the substrate for definition of field oxide regions and active area regions for the n-channel access transistor; subjecting the patterned substrate to oxidizing conditions to form a pair of field oxide regions and an intervening n-channel access transistor active area therebetween, the field oxide regions having respective bird's beak regions extending into the n-channel access transistor active area, the n-channel access transistor active area defining a central region away from the bird's beak regions; and conducting a p-type V.sub.T ion implant into the n-channel active area using the field oxide bird's beak regions as an implant mask to concentrate the V.sub.T implant in the central region of the active area.Type: GrantFiled: February 18, 1997Date of Patent: April 14, 1998Assignee: Micron Technology, Inc.Inventors: Charles H. Dennison, Ken Marr
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Patent number: 5650350Abstract: A semiconductor processing method of forming a static random access memory cell having an n-channel access transistor includes, providing a bulk semiconductor substrate; patterning the substrate for definition of field oxide regions and active area regions for the n-channel access transistor; subjecting the patterned substrate to oxidizing conditions to form a pair of field oxide regions and an intervening n-channel access transistor active area therebetween, the field oxide regions having respective bird's beak regions extending into the n-channel access transistor active area, the n-channel access transistor active area defining a central region away from the bird's beak regions; and conducting a p-type V.sub.T ion implant into the n-channel active area using the field oxide bird's beak region as an implant mask to concentrate the V.sub.T implant in the central region of the active area.Type: GrantFiled: August 11, 1995Date of Patent: July 22, 1997Assignee: Micron Technology, Inc.Inventors: Charles H. Dennison, Ken Marr