Patents by Inventor Ken Patterson

Ken Patterson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8145959
    Abstract: A test system includes a computer and an interface device for accessing a scan chain on an application specific integrated circuit (ASIC) under test. The computer includes a memory that contains application software that when executed by the computer quantifies soft errors and soft error rates (SER) in storage elements on the ASIC. The interface device receives commands and data from the computer, translates the commands and data from a first protocol to a second protocol and communicates the commands and data in the second protocol to the ASIC. A method for measuring SER in the ASIC includes baseline, comparison, and latch up accesses of data in a scan chain in the ASIC. Between accesses, the ASIC is exposed to a neutron flux that accelerates the occurrence of soft errors due to ionizing radiation upon the ASIC.
    Type: Grant
    Filed: October 23, 2009
    Date of Patent: March 27, 2012
    Assignee: Avago Technologies Enterprise IP (Singapore) Pte. Ltd.
    Inventors: Marcus Mims, J. Ken Patterson, Ronald W. Kee
  • Patent number: 7952398
    Abstract: A receiver suitable for applications that desire a common-mode voltage range from approximately 0.7V to approximately 0.9V is arranged by coupling first and second differential pair circuit architectures based on first and second current-steering schemes into the same path to generate an output signal. The receiver includes first and second differential pair circuits. The first differential pair circuit is coupled to a first current-steering path via a first port and a second current-steering path via a second port. The second differential pair circuit is coupled to the first current-steering path via a third port and the second current-steering path via a fourth port. A bridge circuit is interposed between the first and second differential pair circuits. The bridge circuit integrates the first and second current-steering paths in a single-stage of the receiver assembly. A bias signal directs the bridge circuit over a set of worst case conditions.
    Type: Grant
    Filed: April 27, 2007
    Date of Patent: May 31, 2011
    Assignee: Avago Technologies Enterprise IP (Singapore) Pte. Ltd.
    Inventors: Manuel Salcido, J. Ken Patterson, Thomas Edward Cynkar
  • Publication number: 20110099440
    Abstract: A test system includes a computer and an interface device for accessing a scan chain on an application specific integrated circuit (ASIC) under test. The computer includes a memory that contains application software that when executed by the computer quantifies soft errors and soft error rates (SER) in storage elements on the ASIC. The interface device receives commands and data from the computer, translates the commands and data from a first protocol to a second protocol and communicates the commands and data in the second protocol to the ASIC. A method for measuring SER in the ASIC includes baseline, comparison, and latch up accesses of data in a scan chain in the ASIC. Between accesses, the ASIC is exposed to a neutron flux that accelerates the occurrence of soft errors due to ionizing radiation upon the ASIC.
    Type: Application
    Filed: October 23, 2009
    Publication date: April 28, 2011
    Inventors: Marcus Mims, J. Ken Patterson, Ronald W. Kee
  • Publication number: 20080268804
    Abstract: A receiver suitable for applications that desire a common-mode voltage range from approximately 0.7V to approximately 0.9V is arranged by coupling first and second differential pair circuit architectures based on first and second current-steering schemes into the same path to generate an output signal. The receiver includes first and second differential pair circuits. The first differential pair circuit is coupled to a first current-steering path via a first port and a second current-steering path via a second port. The second differential pair circuit is coupled to the first current-steering path via a third port and the second current-steering path via a fourth port. A bridge circuit is interposed between the first and second differential pair circuits. The bridge circuit integrates the first and second current-steering paths in a single-stage of the receiver assembly. A bias signal directs the bridge circuit over a set of worst case conditions.
    Type: Application
    Filed: April 27, 2007
    Publication date: October 30, 2008
    Inventors: Manuel Salcido, J. Ken Patterson, Thomas Edward Cynkar
  • Patent number: 5878455
    Abstract: A corner guard for reinforcing an edge or corner of a mattress of a bed is disclosed. The corner guard is constructed from a flat sheet of material formed into two flat panels intersecting to define a 90 degree primary angle, wherein the panels together further define interior areas facing the mattress and exterior areas facing away from the mattress. Each panel has a tab extending therefrom at right angles toward the interior. Each tab also has a fin extending therefrom toward the primary angle. Fastener openings are provided in each fin and tab. At the intersection of the base of each fin, tab, and panel is a circular cut-out. The corner guard can be punched and formed from metal or molded from polymer.
    Type: Grant
    Filed: January 21, 1998
    Date of Patent: March 9, 1999
    Assignee: Chattam & Wells
    Inventor: Ken Patterson
  • Patent number: D493376
    Type: Grant
    Filed: August 18, 2003
    Date of Patent: July 27, 2004
    Assignee: Edwards Systems Technology, Inc.
    Inventors: Robert Right, Hilario Costa, Ken Patterson