Abstract: In one embodiment, a cache element allocation method is provided. Each cache element on a CPU is assigned a quality rank based on the error rate of the cache element. If an allocated cache element is deemed to be faulty, the quality rank of the faulty allocated cache element is compared with the quality rank of the non-allocated cache elements. If a non-allocated cache element has a lower quality rank than the allocated cache element, the non-allocated cache element is swapped in for the allocated cache element.

Abstract: In one embodiment, a CPU cache management system is provided. The CPU management system includes, for example, a CPU chip and cache management logic. The CPU chip include cache elements that are initially in use and spare cache elements that not initially in use. The cache management logic determines whether currently-used cache elements are faulty. If a cache element is determined to be faulty, the cache management logic schedules a reboot of the computer and swaps in a spare cache element for the faulty currently-used cache element during the reboot.

Abstract: Systems and methods for repairing a processor are provided. In one embodiment, a method for repairing a processor is provided that includes, for example, the steps of initializing and executing an operating system, determining that a cache element is faulty, and swapping in a spare cache element for said faulty cache element while the operating system is executing.

Abstract: Systems and methods for conducting processor health-checks are provided. In one embodiment, a method for evaluating the status of a processor is provided. The method includes, for example, initializing and executing an operating system, de-allocating the processor from the available pool or system resources and performing a health-check on the processor while the operating system is executing.

Abstract: Systems and methods for repairing a processor are provided. In one embodiment, a method for repairing a processor is provided that includes, for example, the steps of initializing and executing an operating system, determining that a cache element is faulty, and swapping in a spare cache element for said faulty cache element while the operating system is executing.

Abstract: Systems and methods for repairing a processor are provided. In one embodiment, a method for repairing a processor is provided that includes, for example, the steps of initializing and executing an operating system, determining that a cache element is faulty, and swapping in a spare cache element for said faulty cache element while the operating system is executing.

Abstract: Systems and methods for conducting processor health-checks are provided. In one embodiment, a method for evaluating the status of a processor is provided. The method includes, for example, initializing and executing an operating system, de-allocating the processor from the available pool or system resources and performing a health-check on the processor while the operating system is executing.

Abstract: In one embodiment, a method for repairing a faulty cache element is provided. Once a monitored cache element is determined to be faulty, the system stores the repair information, and cache configuration in an EEPROM or non-volatile memory on the CPU module. Then the computer is rebooted. During the reboot, the faulty cache element is repaired by being swapped out for a spare cache element based on the information stored in the EEPROM or the non-volatile memory.

Abstract: In one embodiment, a cache element allocation method is provided. Each cache element on a CPU is assigned a quality rank based on the error rate of the cache element. If an allocated cache element is deemed to be faulty, the quality rank of the faulty allocated cache element is compared with the quality rank of the non-allocated cache elements. If a non-allocated cache element has a lower quality rank than the allocated cache element, the non-allocated cache element is swapped in for the allocated cache element.

Abstract: In one embodiment, a CPU cache management system is provided. The CPU management system includes, for example, a CPU chip and cache management logic. The CPU chip include cache elements that are initially in use and spare cache elements that not initially in use. The cache management logic determines whether currently-used cache elements are faulty. If a cache element is determined to be faulty, the cache management logic schedules a reboot of the computer and swaps in a spare cache element for the faulty currently-used cache element during the reboot.

Abstract: Systems and methods for repairing a processor are provided. In one embodiment, a method for repairing a processor is provided that includes, for example, the steps of initializing and executing an operating system, determining that a cache element is faulty, and swapping in a spare cache element for said faulty cache element while the operating system is executing.

Abstract: A method for controlling application of an erasure mode of an error correction code (ECC) algorithm in a memory subsystem includes detecting errors in cache lines retrieved from the memory subsystem using the ECC algorithm. The method also analyzes the errors to detect a repeated bit pattern of data corruption within the cache lines, correlates the detected repeated bit pattern of data corruption to one of a plurality of domains of the memory subsystem, and applies the ECC algorithm to erase bits associated with the detected repeated bit pattern from cache lines retrieved from the correlated domain of the memory subsystem.

Abstract: Systems and methods for repairing a processor are provided. In one embodiment, a method for repairing a processor is provided that includes, for example, the steps of initializing and executing an operating system, determining that a cache element is faulty, and swapping in a spare cache element for said faulty cache element while the operating system is executing.

Abstract: A system utilizing an erasure mode in an error correction code algorithm is described that includes non-volatile memory storing a page deallocation table. A memory controller stores and retrieves data from a memory subsystem, and uses an error correction code algorithm to correct data corruption in retrieved data. An error analysis algorithm executed in a processor records instances of data corruption in the page deallocation tables and deallocates memory regions associated with multiple occurrences of data corruption at single bit locations. The error analysis algorithm further causes the memory controller to apply an erasure mode of the error correction code algorithm upon detection of a repeated pattern of data corruption across different addresses of the memory subsystem, and removes entries in the page deallocation table that correspond to data corruption addressed by application of the erasure mode.

Abstract: In one embodiment, a computer readable medium comprises code for recording occurrences of data corruption in data retrieved from a memory subsystem, code for determining whether bit locations within the memory subsystem are associated with multiple occurrences of data corruption, code for deallocating, in response to the code for determining, memory regions containing bit locations associated with multiple occurrences of data corruption, code for analyzing patterns of data corruption repeated across multiple addresses of the memory subsystem, and code for controlling application of an error correction code (ECC) algorithm by the memory subsystem to erase bits associated with a repeated bit pattern, detected by the code for analyzing, from data retrieved from the memory subsystem.

Abstract: Embodiments of the invention provide a method and apparatus for automatically evaluating and allocating resources in a cell based system. In one method embodiment, the present invention receives a request to generate a cell based system of resources. A list of allocatable resources having corresponding evaluation data is then accessed. The request for the cell based system is then compared with the list of allocatable resources having corresponding evaluation data. The allocatable resources are then assigned to the cell based system.

Abstract: Embodiments of the invention provide a method and apparatus for selecting a primary resource in a redundant subsystem. In one method embodiment, the present invention receives a list of available resources for a redundant subsystem. Additionally, the available resources are tested and results of the testing are generated. Then, the primary resource is selected for the subsystem based on the results of the testing.

Abstract: A microprocessor includes a plurality of execution units of a same type, and a first register operable to select between a first and a second mode of operation, wherein the microprocessor utilizes at least one of the execution units as a redundant execution unit during the first mode of operation and utilizes none of the execution units as a redundant execution unit during the second mode of operation.

Abstract: In one embodiment, a CPU cache management system is provided. The CPU management system includes, for example, a CPU chip and cache management logic. The CPU chip include cache elements that are initially in use and spare cache elements that not initially in use. The cache management logic determines whether currently-used cache elements are faulty. If a cache element is determined to be faulty, the cache management logic schedules a reboot of the computer and swaps in a spare cache element for the faulty currently-used cache element during the reboot.

Abstract: Systems and methods for repairing a processor are provided. In one embodiment, a method for repairing a processor is provided that includes, for example, the steps of initializing and executing an operating system, determining that a cache element is faulty, and swapping in a spare cache element for said faulty cache element while the operating system is executing.