Patents by Inventor Ken W. Marr
Ken W. Marr has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6934209Abstract: A T-RAM memory cell includes a temperature compensation device to adjust the gate-to-source voltage of an access transistor for the memory cell as a function of temperature so that the sub-threshold current of the transistor is insensitive to temperature variations. As a result, the sub-threshold current can be maintained slightly above the holding current of a thyristor used in the memory cell despite substantial temperature variations. In one embodiment, the temperature compensation device includes a current source directing a fixed current through a diode-connected transistor of the type used as the memory cell access transistor. Temperature induced changes in a reference voltage generated at the junction between the current source and the transistor therefore match the temperature induced changed in the sub-threshold current of the access transistor.Type: GrantFiled: March 31, 2003Date of Patent: August 23, 2005Assignee: Micron Technology, Inc.Inventor: Ken W. Marr
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Patent number: 6829156Abstract: A power-up circuit for an SRAM, particularly a loadless 4-T SRAM cell having PMOS access transistors. The power-up circuit disables a current path to the digit lines in an array of SRAM cells during power-up of the SRAM. As a result, the SRAM cells cannot draw power from the digit lines during power-up if voltages on word lines in the array during power-up cause access transistors for the SRAM cells to become conductive.Type: GrantFiled: January 21, 2003Date of Patent: December 7, 2004Assignee: Micron Technology, Inc.Inventor: Ken W. Marr
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Patent number: 6781907Abstract: A T-RAM memory cell includes a temperature compensation device to adjust the gate-to-source voltage of an access transistor for the memory cell as a function of temperature so that the sub-threshold current of the transistor is insensitive to temperature variations. As a result, the sub-threshold current can be maintained slightly above the holding current of a thyristor used in the memory cell despite substantial temperature variations. In one embodiment, the temperature compensation device includes a current source directing a fixed current through a diode-connected transistor of the type used as the memory cell access transistor. Temperature induced changes in a reference voltage generated at the junction between the current source and the transistor therefore match the temperature induced changed in the sub-threshold current of the access transistor.Type: GrantFiled: June 6, 2002Date of Patent: August 24, 2004Assignee: Micron Technology, Inc.Inventor: Ken W. Marr
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Patent number: 6731546Abstract: A power-up circuit for an SRAM, particularly a loadless 4-T SRAM cell having PMOS access transistors. The power-up circuit disables a current path to the digit lines in an array of SRAM cells during power-up of the SRAM. As a result, the SRAM cells cannot draw power from the digit lines during power-up if voltages on word lines in the array during power-up cause access transistors for the SRAM cells to become conductive.Type: GrantFiled: January 21, 2003Date of Patent: May 4, 2004Assignee: Micron Technology, Inc.Inventor: Ken W. Marr
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Patent number: 6717866Abstract: A power-up circuit for an SRAM, particularly a loadless 4-T SRAM cell having PMOS access transistors. The power-up circuit disables a current path to the digit lines in an array of SRAM cells during power-up of the SRAM. As a result, the SRAM cells cannot draw power from the digit lines during power-up if voltages on word lines in the array during power-up cause access transistors for the SRAM cells to become conductive.Type: GrantFiled: January 21, 2003Date of Patent: April 6, 2004Assignee: Micron Technology, Inc.Inventor: Ken W. Marr
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Patent number: 6717867Abstract: A power-up circuit for an SRAM, particularly a loadless 4-T SRAM cell having PMOS access transistors. The power-up circuit disables a current path to the digit lines in an array of SRAM cells during power-up of the SRAM. As a result, the SRAM cells cannot draw power from the digit lines during power-up if voltages on word lines in the array during power-up cause access transistors for the SRAM cells to become conductive.Type: GrantFiled: January 21, 2003Date of Patent: April 6, 2004Assignee: Micron Technology, Inc.Inventor: Ken W. Marr
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Patent number: 6707707Abstract: A power-up circuit for an SRAM, particularly a loadless 4-T SRAM cell having PMOS access transistors. The power-up circuit disables a current path to the digit lines in an array of SRAM cells during power-up of the SRAM. As a result, the SRAM cells cannot draw power from the digit lines during power-up if voltages on word lines in the array during power-up cause access transistors for the SRAM cells to become conductive.Type: GrantFiled: December 21, 2001Date of Patent: March 16, 2004Assignee: Micron Technology, Inc.Inventor: Ken W. Marr
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Publication number: 20030227790Abstract: A T-RAM memory cell includes a temperature compensation device to adjust the gate-to-source voltage of an access transistor for the memory cell as a function of temperature so that the sub-threshold current of the transistor is insensitive to temperature variations. As a result, the sub-threshold current can be maintained slightly above the holding current of a thyristor used in the memory cell despite substantial temperature variations. In one embodiment, the temperature compensation device includes a current source directing a fixed current through a diode-connected transistor of the type used as the memory cell access transistor. Temperature induced changes in a reference voltage generated at the junction between the current source and the transistor therefore match the temperature induced changed in the sub-threshold current of the access transistor.Type: ApplicationFiled: March 31, 2003Publication date: December 11, 2003Inventor: Ken W. Marr
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Publication number: 20030227792Abstract: A T-RAM memory cell includes a temperature compensation device to adjust the gate-to-source voltage of an access transistor for the memory cell as a function of temperature so that the sub-threshold current of the transistor is insensitive to temperature variations. As a result, the sub-threshold current can be maintained slightly above the holding current of a thyristor used in the memory cell despite substantial temperature variations. In one embodiment, the temperature compensation device includes a current source directing a fixed current through a diode-connected transistor of the type used as the memory cell access transistor. Temperature induced changes in a reference voltage generated at the junction between the current source and the transistor therefore match the temperature induced changed in the sub-threshold current of the access transistor.Type: ApplicationFiled: June 6, 2002Publication date: December 11, 2003Inventor: Ken W. Marr
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Publication number: 20030133342Abstract: A power-up circuit for an SRAM, particularly a loadless 4-T SRAM cell having PMOS access transistors. The power-up circuit disables a current path to the digit lines in an array of SRAM cells during power-up of the SRAM. As a result, the SRAM cells cannot draw power from the digit lines during power-up if voltages on word lines in the array during power-up cause access transistors for the SRAM cells to become conductive.Type: ApplicationFiled: January 21, 2003Publication date: July 17, 2003Inventor: Ken W. Marr
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Publication number: 20030133343Abstract: A power-up circuit for an SRAM, particularly a loadless 4-T SRAM cell having PMOS access transistors. The power-up circuit disables a current path to the digit lines in an array of SRAM cells during power-up of the SRAM. As a result, the SRAM cells cannot draw power from the digit lines during power-up if voltages on word lines in the array during power-up cause access transistors for the SRAM cells to become conductive.Type: ApplicationFiled: January 21, 2003Publication date: July 17, 2003Inventor: Ken W. Marr
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Publication number: 20030133341Abstract: A power-up circuit for an SRAM, particularly a loadless 4-T SRAM cell having PMOS access transistors. The power-up circuit disables a current path to the digit lines in an array of SRAM cells during power-up of the SRAM. As a result, the SRAM cells cannot draw power from the digit lines during power-up if voltages on word lines in the array during power-up cause access transistors for the SRAM cells to become conductive.Type: ApplicationFiled: January 21, 2003Publication date: July 17, 2003Inventor: Ken W. Marr
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Publication number: 20030128595Abstract: A power-up circuit for an SRAM, particularly a loadless 4-T SRAM cell having PMOS access transistors. The power-up circuit disables a current path to the digit lines in an array of SRAM cells during power-up of the SRAM. As a result, the SRAM cells cannot draw power from the digit lines during power-up if voltages on word lines in the array during power-up cause access transistors for the SRAM cells to become conductive.Type: ApplicationFiled: January 21, 2003Publication date: July 10, 2003Inventor: Ken W. Marr
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Publication number: 20030117833Abstract: A power-up circuit for an SRAM, particularly a loadless 4-T SRAM cell having PMOS access transistors. The power-up circuit disables a current path to the digit lines in an array of SRAM cells during power-up of the SRAM. As a result, the SRAM cells cannot draw power from the digit lines during power-up if voltages on word lines in the array during power-up cause access transistors for the SRAM cells to become conductive.Type: ApplicationFiled: December 21, 2001Publication date: June 26, 2003Inventor: Ken W. Marr
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Patent number: 6496422Abstract: The present invention is a current-mirror-based bias generator for a load less four transistor SRAM as well as associated methods of controlling or modifying the current conducted by the access transistors of such an SRAM. The present invention may be thought of as an adjustable temperature coefficient, bias generator that references, via a current mirror, a reference bank of SRAM cells. The bank of reference cells provides an indication of the necessary conduction characteristics (e.g., gate to source voltage) of the access transistors under various conditions. By applying a bias voltage to the word line the desired current is sourced from the digit line. The bank of reference SRAM cells inherently compensates for process variations. The adjustable temperature coefficient bias generator allows the current sourced by the digit lines to vary greatly as a result of temperature variations. Thus, the present invention compensates for both process variations and temperature variations.Type: GrantFiled: December 8, 2000Date of Patent: December 17, 2002Assignee: Micron Technology, Inc.Inventor: Ken W. Marr
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Patent number: 6388933Abstract: The present invention is a current-mirror-based bias generator for a load less four transistor SRAM as well as associated methods of controlling or modifying the current conducted by the access transistors of such an SRAM. The present invention may be thought of as an adjustable temperature coefficient, bias generator that references, via a current mirror, a reference bank of SRAM cells. The bank of reference cells provides an indication of the necessary conduction characteristics (e.g., gate to source voltage) of the access transistors under various conditions. By applying a bias voltage to the word line the desired current is sourced from the digit line. The bank of reference SRAM cells inherently compensates for process variations. The adjustable temperature coefficient bias generator allows the current sourced by the digit lines to vary greatly as a result of temperature variations. Thus, the present invention compensates for both process variations and temperature variations.Type: GrantFiled: December 8, 2000Date of Patent: May 14, 2002Assignee: Micron Technology, Inc.Inventor: Ken W. Marr
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Patent number: 6373756Abstract: The present invention is a current-mirror-based bias generator for a load less four transistor SRAM as well as associated methods of controlling or modifying the current conducted by the access transistors of such an SRAM. The present invention may be thought of as an adjustable temperature coefficient, bias generator that references, via a current mirror, a reference bank of SRAM cells. The bank of reference cells provides an indication of the necessary conduction characteristics (e.g., gate to source voltage) of the access transistors under various conditions. By applying a bias voltage to the word line the desired current is sourced from the digit line. The bank of reference SRAM cells inherently compensates for process variations. The adjustable temperature coefficient bias generator allows the current sourced by the digit lines to vary greatly as a result of temperature variations. Thus, the present invention compensates for both process variations and temperature variations.Type: GrantFiled: December 8, 2000Date of Patent: April 16, 2002Assignee: Micron Technology, Inc.Inventor: Ken W. Marr
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Patent number: 6337813Abstract: The present invention is a current-mirror-based bias generator for a load less four transistor SRAM as well as associated methods of controlling or modifying the current conducted by the access transistors of such an SRAM. The present invention may be thought of as an adjustable temperature coefficient, bias generator that references, via a current mirror, a reference bank of SRAM cells. The bank of reference cells provides an indication of the necessary conduction characteristics (e.g., gate to source voltage) of the access transistors under various conditions. By applying a bias voltage to the word line the desired current is sourced from the digit line. The bank of reference SRAM cells inherently compensates for process variations. The adjustable temperature coefficient bias generator allows the current sourced by the digit lines to vary greatly as a result of temperature variations. Thus, the present invention compensates for both process variations and temperature variations.Type: GrantFiled: December 8, 2000Date of Patent: January 8, 2002Assignee: Micron Technology, Inc.Inventor: Ken W. Marr
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Publication number: 20010054740Abstract: An apparatus includes a first doped region, a first doped well, a first doped plug, a second doped plug, and an isolation structure. The first doped well is disposed within the first doped region. The first doped plug is disposed within the first doped well. The second doped plug is disposed within the first doped region. The isolation structure is disposed between the first and second doped plugs. A method includes providing a first doped region. A first doped well is formed within the first doped region, and a first doped plug is formed within the first doped well. A second doped plug is formed within the first doped region, and an isolation structure is formed between the first and second doped plugs.Type: ApplicationFiled: August 20, 2001Publication date: December 27, 2001Applicant: Micron Technology, Inc.Inventor: Ken W. Marr
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Patent number: 6330195Abstract: The present invention is a current-mirror-based bias generator for a load less four transistor SRAM as well as associated methods of controlling or modifying the current conducted by the access transistors of such an SRAM. The present invention may be thought of as an adjustable temperature coefficient, bias generator that references, via a current mirror, a reference bank of SRAM cells. The bank of reference cells provides an indication of the necessary conduction characteristics (e.g., gate to source voltage) of the access transistors under various conditions. By applying a bias voltage to the word line the desired current is sourced from the digit line. The bank of reference SRAM cells inherently compensates for process variations. The adjustable temperature coefficient bias generator allows the current sourced by the digit lines to vary greatly as a result of temperature variations. Thus, the present invention compensates for both process variations and temperature variations.Type: GrantFiled: December 8, 2000Date of Patent: December 11, 2001Assignee: Micron Technology, Inc.Inventor: Ken W. Marr