Abstract: A display controller includes a first chip and a second chip. The first chip is configured to control a display device. The second chip is externally coupled to the first chip, and configured to be a random access memory and. The first chip is further configured to provide a first supply power to the second chip and to access the second chip during the controlling of the display device.

Abstract: An interface of a memory circuit includes a chip enable terminal, at least one data terminal, and a data strobe terminal. The chip enable terminal receives a chip enable signal that varies between a first high voltage and a low voltage. The at least one data terminal receives a first data signal that varies between a second high voltage and the low voltage during a command phase, and transmits or receives a second data signal during a data phase. The data strobe terminal receives a first data strobe signal that periodically varies between the second high voltage and the low voltage during the command phase, and transmits or receives a second data strobe signal that swings periodically during the data phase. During a transition interval between the command phase and the data phase, the data strobe terminal stops receiving or transmitting data strobe signals that swing periodically.

Abstract: An interface of a memory circuit includes a chip enable terminal, at least one data terminal, and a data strobe terminal. The chip enable terminal receives a chip enable signal that varies between a first high voltage and a low voltage for enabling the memory circuit. The at least one data terminal receives at least one first data signal that varies between a second high voltage and the low voltage. The data strobe terminal receives a first data strobe signal that periodically varies between the second high voltage and the low voltage. The first data strobe signal is synchronized with the at least one first data signal, and is arranged to latch and sample the at least one first data signal. The first high voltage is higher than the second high voltage, and the second high voltage is higher than the low voltage.

Abstract: A device of correcting duty cycle includes: a duty cycle correcting circuit, a controller of the duty cycle correcting circuit and a duty cycle detecting circuit. The duty cycle correcting circuit generates a pair of phase-shifting clocks in accordance with a pair of complementary clocks and regenerates a regenerated clock in accordance with the pair of phase-shifting clocks. The controller of the duty cycle correcting circuit couples to the duty cycle correcting circuit. The duty cycle detecting circuit couples to the duty cycle correcting circuit and the controller of the duty cycle correcting circuit, and generates a detecting output to the controller of the duty cycle correcting circuit in accordance with a current duty cycle of the regenerated clock. The controller of the duty cycle correcting circuit controls the duty cycle correcting circuit in accordance with the detecting output to adjust the pair of phase-shifting clocks.

Abstract: A device of correcting duty cycle includes: a duty cycle correcting circuit, a controller of the duty cycle correcting circuit and a duty cycle detecting circuit. The duty cycle correcting circuit generates a pair of phase-shifting clocks in accordance with a pair of complementary clocks and regenerates a regenerated clock in accordance with the pair of phase-shifting clocks. The controller of the duty cycle correcting circuit couples to the duty cycle correcting circuit. The duty cycle detecting circuit couples to the duty cycle correcting circuit and the controller of the duty cycle correcting circuit, and generates a detecting output to the controller of the duty cycle correcting circuit in accordance with a current duty cycle of the regenerated clock. The controller of the duty cycle correcting circuit controls the duty cycle correcting circuit in accordance with the detecting output to adjust the pair of phase-shifting clocks.

Abstract: A display controller includes a first chip and a second chip. The first chip is configured to control a display device. The second chip is externally coupled to the first chip, and configured to be a random access memory and. The first chip is further configured to provide a first supply power to the second chip and to access the second chip during the controlling of the display device.

Abstract: An interface of a memory circuit includes a chip enable terminal, at least one data terminal, and a data strobe terminal. The chip enable terminal receives a chip enable signal that varies between a first high voltage and a low voltage for enabling the memory circuit. The at least one data terminal receives at least one first data signal that varies between a second high voltage and the low voltage. The data strobe terminal receives a first data strobe signal that periodically varies between the second high voltage and the low voltage. The first data strobe signal is synchronized with the at least one first data signal, and is arranged to latch and sample the at least one first data signal. The first high voltage is higher than the second high voltage, and the second high voltage is higher than the low voltage.