Abstract: Methods and systems for incorporating captured live event data into one or more virtual environments are described. For instance, a system can include a plurality of digital video capturing devices configured to capture real-time events that occur during a plurality of live events in respective live environments to generate real-time multimedia data. A computing system can receive the real-time multimedia data, generate virtual multimedia data, and incorporate the real-time multimedia data and the virtual multimedia data to generate hybrid multimedia data for a plurality of hybrid events in respective hybrid environments such that the hybrid events occur substantially simultaneously with the real-time events. A user interface is displayed on a mobile electronic device which presents the hybrid environments.

Abstract: Methods and systems for incorporating captured live event data into one or more virtual environments are described. For instance, a system can include a plurality of digital video capturing devices configured to capture real-time events that occur during a plurality of live events in respective live environments to generate real-time multimedia data. A computing system can receive the real-time multimedia data, generate virtual multimedia data, and incorporate the real-time multimedia data and the virtual multimedia data to generate hybrid multimedia data for a plurality of hybrid events in respective hybrid environments such that the hybrid events occur substantially simultaneously with the real-time events. A user interface is displayed on a mobile electronic device which presents the hybrid environments.

Abstract: A technique includes locking a locked loop circuit onto a reference clock signal. The locking includes locking the lock loop circuit onto the reference clock signal in response to a first feedback signal provided by a first feedback path and locking the locked loop circuit onto the reference clock signal in response to a second feedback signal that is provided by a second feedback path.

Abstract: In general, in one aspect, the disclosure describes a phase-locked loop circuit. The circuit includes an oscillator having a first control input, a second control input, and a third control input, wherein the first control input, the second control input, and the third control input act to control output frequency of the oscillator. The circuit further includes a first charge pump and a second charge pump. A first bias generator is coupled to the first control input of the oscillator and can receive electrical input from the first charge pump. A second bias generator is coupled to the second control input of the oscillator and can receive electrical input from the first charge pump, the second charge pump, and the first bias generator. A third bias generator is coupled to the third control input of the oscillator and can receive electrical input from the second charge pump and the first bias generator.

Abstract: In some embodiments, a clock generator is provided that provides a generator clock. The clock generator comprises a first clock source to provide a first clock and a second clock source to provide a second clock whose frequency at least indirectly tracks a supply to a clock distribution network. The clock generator selectably provides as the generator clock the first clock when the second clock leads the first clock and the second clock when it lags behind the first clock. Other embodiments are claimed and disclosed herein.

Abstract: A method and apparatus for a frequency-based slope-adjustment circuit block are described herein.

Abstract: In general, in one aspect, the disclosure describes a phase-locked loop circuit. The circuit includes an oscillator having a first control input and a second control input, wherein the first control input and the second control input act to control output frequency of the oscillator. The circuit further includes a first charge pump and a second charge pump. A first bias generator is coupled to the first control input of the oscillator and can receive electrical input from the first charge pump and the second charge pump. A second bias generator is coupled to the second control input of the oscillator and can receive electrical input from the second charge pump and the first bias generator.

Abstract: A method and apparatus for a frequency-based slope-adjustment circuit block are described herein.

Abstract: An embodiment of the present invention is a technique to control clock distribution to a circuit. A scheduler schedules a sequence of a clock distribution of clock signals to a plurality of clock distribution domains (CKDOMs) in the circuit according to a state status of the circuit. A controller controls enabling the clock distribution to the CKDOMs according to the scheduled sequence.

Abstract: In one embodiment, there is provided a method comprising determining a target operating point for an electronic device, the target operating point including a target operating frequency and a target operating voltage; and dynamically changing a current operating point for the electronic device including a current operating frequency and a current operating voltage by non-contemporaneously changing the current operating frequency to the target operating frequency and a current operating voltage to the target operating voltage, wherein during the changing the electronic device is in an active state.

Abstract: A method, an apparatus, and a system for phase jitter measurement circuits are described herein.

Abstract: A method and apparatus for jitter reduction in a Phase Locked Loop (PLL) that includes determining a size of a original charge pump adequate to generate an appropriate control voltage to a Voltage Controlled Oscillator (VCO) of a PLL based on the charge pump receiving a single up signal or down signal within one cycle of a PLL input reference clock. N number of the up signal or down signal are generated to a second charge pump 1/N the size of the original charge pump. The N number of the up signal or the down signal occurs within one cycle of the PLL input reference clock. The second charge pump generates N second control voltage corrections each being 1/N the amplitude of the appropriate control voltage glitch, thus minimizing glitches on the second control voltages and reducing jitter to the VCO.

Abstract: In one embodiment, there is provided a method comprising determining a target operating point for an electronic device, the target operating point including a target operating frequency and a target operating voltage; and dynamically changing a current operating point for the electronic device including a current operating frequency and a current operating voltage by non-contemporaneously changing the current operating frequency to the target operating frequency and a current operating voltage to the target operating voltage, wherein during the changing the electronic device is in an active state.

Abstract: According to embodiments of the present invention, a phase-locked loop (PLL) may include circuitry to select a wide pulse width for the phase-frequency detector control signal when the PLL is in a frequency acquisition stage, a narrow pulse width for the phase-frequency detector control signal when the PLL is in a phase capture stage, and a wide pulse width of the phase-frequency detector control signal when the PLL is in a lock stage.

Abstract: An apparatus and method for calibrating a delay element is described herein.

Abstract: A self-biased phase locked loop (PLL) circuit includes a charge pump to generate a control voltage, a controlled oscillator coupled to the charge pump to generate the output signal based at least in part upon the control voltage, discharge circuitry coupled to the charge pump to discharge the control voltage, and frequency detection circuitry coupled to the controlled oscillator and the discharge circuitry to generate a digital feedback signal for terminating discharge of the control voltage by the discharge circuitry when the output signal reaches a threshold frequency that is a fraction of the target frequency.

Abstract: A system and method for inputting Chinese characters using Pinyin without requiring the entry of a delimiter key between Pinyin entries in a reduced keyboard is disclosed. The system searches for all possible single or multiple Pinyin spellings based on the entered Latin alphabets. Once the user has completed the inputting of the Pinyin spellings for desired Chinese phrase or characters, all possible matching phrases or characters are displayed on screen and off-screen due to screen size. The user then scrolls through a list of matching phrases or characters and selects the desired one by clicking.