Abstract: A shift register having a plurality of circuit cells successively connected in a chain formation is proposed. Each of the circuit cells includes a first inversion gate, a first transmission gate, connected to an output of the first inversion gate, being switched by a clock, and a second inversion gate connected to an output of the first transmission gate. The circuit cell further includes a first P-channel transistor, connected between an output of the second inversion gate and an input of the first inversion gate, being switched by the clock, a second transmission gate, connected to the output of the second inversion gate, being switched by an inversion clock, and a second P-channel transistor, connected to the output of the first transmission gate, being switched by the inversion clock.

Abstract: According to the present invention, there is also provided a field gate array comprising a matrix of logic cells each having n input terminals, a plurality of intercell buses disposed between the logic cells and each having a plurality of intercell signal lines, and programmable junctions disposed around the logic cells and each including the intercell signal lines, n input terminal lines intersecting with the intercell signal lines and connected to the input terminals, and programmable switches disposed at intersections between the intercell signal lines and the input terminal lines, the switches being placed at positions for connecting n of the first signal lines to at least one combination of the n input terminal lines and for connecting optional m (m<n) of the intercell signal lines simultaneously to any of the input terminal lines. With the above arrangement, the junction comprises a minimum number of switches and hence has as small an area as possible.

Abstract: A shift register having a plurality of circuit cells successively connected in a chain formation is proposed. Each of the circuit cells includes a first inversion gate, a first transmission gate, connected to an output of the first inversion gate, being switched by a clock, and a second inversion gate connected to an output of the first transmission gate. The circuit cell further includes a first P-channel transistor, connected between an output of the second inversion gate and an input of the first inversion gate, being switched by the clock, a second transmission gate, connected to the output of the second inversion gate, being switched by an inversion clock, and a second P-channel transistor, connected to the output of the first transmission gate, being switched by the inversion clock.

Abstract: A programmable logic circuit is provided with a plurality of logic cells including specific logic cells, at least two sub blocks, included in the specific logic cell, respectively having two or more inputs and one or more outputs and having only a predetermined combinational logic function by itself, and a switching circuit, included in the specific logic cell, and capable of independently connecting a path between the input and output of each sub block. An arbitrary combinational logic function and an arbitrary sequential logic function are realized by programming ON/OFF states of the switching circuit.