Abstract: A shift register includes stages each constituted by a unit circuit provided with a thin-film transistor (separation transistor) that separates a control node into an output-side first control node and an input-side second control node and a capacitor whose first end is connected to the second control node. The thin-film transistor (separation transistor) has a control terminal that is supplied with a high-level DC power supply voltage. Typically, the channel width of a thin-film transistor (first output control transistor) that controls output from a unit circuit is ten or more times greater than the channel width of the thin-film transistor (separation transistor).

Abstract: A set circuit in a unit circuit in a gate driver of a display device includes a setting transistor, a first auxiliary transistor, and a second auxiliary transistor. The setting transistor includes a source terminal connected to an internal node, a gate terminal connected to a set input terminal, and a drain terminal connected to the set input terminal via the first auxiliary transistor and also connected to an input terminal via the second auxiliary transistor in a diode-connected form. Each transistor is controlled to be in an on state and an off state during normal drive and is controlled to be in the off state and the on state during a pause period by a control signal supplied to the input terminal.

Abstract: A resin composition contains a maleimide compound (I) that is the product of a reaction between a diamine (a-1) derived from a dimer acid and maleic anhydride, and a reactive polycarboxylic acid resin (II) that is the product of a reaction between a reactive epoxycarboxylate resin, the reactive epoxycarboxylate resin being the product of a reaction between an epoxy resin (b-1) and a compound (b-2) having a polymerizable ethylenically unsaturated group and a carboxy group together in one molecule, and a polybasic acid anhydride (b-3).

Abstract: The present application provides a resin-molded capacitor such that heat generated by a capacitor element can be efficiently dissipated, and a power conversion device. The resin-molded capacitor includes a first bus bar and a second bus bar joined to a first capacitor electrode and a second capacitor electrode respectively of a capacitor element, an insulating member joined to at least one of the first capacitor electrode and the second capacitor electrode or at least one of the first bus bar and the second bus bar, and an electrically conductive member joined to the insulating member.

Abstract: In order to achieve small noise and small vibration, as well as a small size and a low cost in a power converter including a capacitor module, there is provided a power converter including a power module and a capacitor module. The capacitor module includes: a plurality of capacitor elements each having a flat wound surface; an exterior case; a resin filler; and a restraint point. The exterior case has arranged therein an inclusion serving as a beam in a direction orthogonal to a flat wound surface of at least one capacitor element of the plurality of capacitor elements, and the at least one capacitor element, and the restraint point is arranged substantially in front of the flat wound surface via the inclusion.

Abstract: The present application provides a resin-molded capacitor such that heat generated by a capacitor element can be efficiently dissipated, and a power conversion device. The resin-molded capacitor includes a first bus bar and a second bus bar joined to a first capacitor electrode and a second capacitor electrode respectively of a capacitor element, an insulating member joined to at least one of the first capacitor electrode and the second capacitor electrode or at least one of the first bus bar and the second bus bar, and an electrically conductive member joined to the insulating member.

Abstract: In order to achieve small noise and small vibration, as well as a small size and a low cost in a power converter including a capacitor module, there is provided a power converter including a power module and a capacitor module. The capacitor module includes: a plurality of capacitor elements each having a flat wound surface; an exterior case; a resin filler; and a restraint point. The exterior case has arranged therein an inclusion serving as a beam in a direction orthogonal to a flat wound surface of at least one capacitor element of the plurality of capacitor elements, and the at least one capacitor element, and the restraint point is arranged substantially in front of the flat wound surface via the inclusion.

Abstract: In a power conversion apparatus including first to fourth semiconductor switching elements connected in series across both terminals of a high voltage-side capacitor, the third and fourth semiconductor switching elements are connected across both terminals of a low voltage-side capacitor via a reactor, and both terminals of the second and third semiconductor switching elements are connected across a charging-discharging capacitor. This charging-discharging capacitor includes a plurality of capacitor elements connected in parallel via a first wiring and a second wiring. Inductance components or capacitance components of the plurality of capacitor elements when viewed from an outflow-inflow portion of the first wiring and an outflow-inflow portion of the second wiring are different from each other such that the charging-discharging capacitor does not have a parallel resonance point in a driving frequency band but has a parallel resonance point in a noise frequency band.

Abstract: In a power conversion apparatus including first to fourth semiconductor switching elements connected in series across both terminals of a high voltage-side capacitor, the third and fourth semiconductor switching elements are connected across both terminals of a low voltage-side capacitor via a reactor, and both terminals of the second and third semiconductor switching elements are connected across a charging-discharging capacitor. This charging-discharging capacitor includes a plurality of capacitor elements connected in parallel via a first wiring and a second wiring. Inductance components or capacitance components of the plurality of capacitor elements when viewed from an outflow-inflow portion of the first wiring and an outflow-inflow portion of the second wiring are different from each other such that the charging-discharging capacitor does not have a parallel resonance point in a driving frequency band but has a parallel resonance point in a noise frequency band.

Abstract: A 3D decoding apparatus according to the present invention includes: a decoding unit which decodes left-eye and right-eye code signals to generate left-eye and right-eye decode signals; an error determining unit which determines an error of the left-eye and the right-eye code signals; an output determining unit which determines, when there is an error in one of the left-eye and the right-eye code signals, whether the one of the code signals that is determined as including an error has an error data mount equal to or greater than a first threshold; and an output unit which outputs neither the left-eye nor the right-eye code signal when the error data amount is smaller than the first threshold, and outputs only the decode signal obtained by decoding the other of the code signals when the error data amount is equal to or greater than the first threshold.

Abstract: A 3D video processing apparatus according to an aspect of the present invention includes an offset value complementing unit which complements an offset value of the first picture, by assigning a value which is equal to or greater than the first offset value and equal to or smaller than the second offset value, the first offset value representing the smaller one of the offset value assigned to the second picture temporally preceding the first picture and the offset value assigned to the third picture temporally succeeding the first picture, and the second offset value representing the larger one of the offset value assigned to the second picture and the offset value assigned to the third picture.

Abstract: A 3D video processor that outputs a left-eye image and a right-eye image to be superimposed on main video includes: a left-eye object processing unit that outputs the left-eye image; a right-eye object processing unit that outputs the right-eye image; and an image output control unit that controls the left-eye object processing unit and the right-eye object processing unit so that the images are synchronously outputted. The left-eye object processing unit determines if image output preparation of the left-eye image is completed. The right-eye object processing unit determines if image output preparation of the right-eye image is completed. The image output control unit instructs to skip the output of both the images, when the image output preparation of one of the left-eye image and the right-eye image is not completed.

Abstract: A 3D decoding apparatus according to the present invention includes: a decoding unit which decodes left-eye and right-eye code signals to generate left-eye and right-eye decode signals; an error determining unit which determines an error of the left-eye and the right-eye code signals; an output determining unit which determines, when there is an error in one of the left-eye and the right-eye code signals, whether the one of the code signals that is determined as including an error has an error data mount equal to or greater than a first threshold; and an output unit which outputs neither the left-eye nor the right-eye code signal when the error data amount is smaller than the first threshold, and outputs only the decode signal obtained by decoding the other of the code signals when the error data amount is equal to or greater than the first threshold.

Abstract: A 3D decoding apparatus according to the present invention includes: a decoding unit which decodes left-eye and right-eye code signals to generate left-eye and right-eye decode signals; an error determining unit which determines an error of the left-eye and the right-eye code signals; an output determining unit which determines, when there is an error in one of the left-eye and the right-eye code signals, whether the one of the code signals that is determined as including an error has an error data mount equal to or greater than a first threshold; and an output unit which outputs neither the left-eye nor the right-eye code signal when the error data amount is smaller than the first threshold, and outputs only the decode signal obtained by decoding the other of the code signals when the error data amount is equal to or greater than the first threshold.

Abstract: A 3D video processor that outputs a left-eye image and a right-eye image to be superimposed on main video includes: a left-eye object processing unit that outputs the left-eye image; a right-eye object processing unit that outputs the right-eye image; and an image output control unit that controls the left-eye object processing unit and the right-eye object processing unit so that the images are synchronously outputted. The left-eye object processing unit determines if image output preparation of the left-eye image is completed. The right-eye object processing unit determines if image output preparation of the right-eye image is completed. The image output control unit instructs to skip the output of both the images, when the image output preparation of one of the left-eye image and the right-eye image is not completed.

Abstract: A 3D video processor that outputs a left-eye image and a right-eye image to be superimposed on main video includes: a left-eye object processing unit that outputs the left-eye image; a right-eye object processing unit that outputs the right-eye image; and an image output control unit that controls the left-eye object processing unit and the right-eye object processing unit so that the left-eye image and the right-eye image are synchronously outputted. The left-eye object processing unit determines whether or not image output preparation of the left-eye image is completed. The right-eye object processing unit determines whether or not image output preparation of the right-eye image is completed. The image output control unit instructs to skip the output of both the left-eye image and the right-eye image, when the image output preparation of one of the left-eye image and the right-eye image is not completed.

Abstract: A 3D decoding apparatus according to the present invention includes: a decoding unit which decodes left-eye and right-eye code signals to generate left-eye and right-eye decode signals; an error determining unit which determines an error of the left-eye and the right-eye code signals; an output determining unit which determines, when there is an error in one of the left-eye and the right-eye code signals, whether the one of the code signals that is determined as including an error has an error data mount equal to or greater than a first threshold; and an output unit which outputs neither the left-eye nor the right-eye code signal when the error data amount is smaller than the first threshold, and outputs only the decode signal obtained by decoding the other of the code signals when the error data amount is equal to or greater than the first threshold.

Abstract: A 3D video processing apparatus according to an aspect of the present invention includes an offset value complementing unit which complements an offset value of the first picture, by assigning a value which is equal to or greater than the first offset value and equal to or smaller than the second offset value, the first offset value representing the smaller one of the offset value assigned to the second picture temporally preceding the first picture and the offset value assigned to the third picture temporally succeeding the first picture, and the second offset value representing the larger one of the offset value assigned to the second picture and the offset value assigned to the third picture.

Abstract: A 3D video processor that outputs a left-eye image and a right-eye image to be superimposed on main video includes: a left-eye object processing unit that outputs the left-eye image; a right-eye object processing unit that outputs the right-eye image; and an image output control unit that controls the left-eye object processing unit and the right-eye object processing unit so that the left-eye image and the right-eye image are synchronously outputted. The left-eye object processing unit determines whether or not image output preparation of the left-eye image is completed. The right-eye object processing unit determines whether or not image output preparation of the right-eye image is completed. The image output control unit instructs to skip the output of both the left-eye image and the right-eye image, when the image output preparation of one of the left-eye image and the right-eye image is not completed.

Abstract: A video decoding apparatus (100) according to an implementation of the present invention includes: a dummy-packet inserting unit (105A) which inserts a dummy packet (221) into a boundary between a section (TS1) and a section (TS2) in a video stream (131); a DEMUX unit (106) which separates a video stream (132) into which the dummy packet (221) is inserted, into visual streams (133 and 135) and audio streams (134 and 136); a seamless detection unit (107) which detects a position at which the dummy packet (221) is inserted, as the boundary in the visual streams (133 and 135) and the audio streams (134 and 136); and a decoding unit (109) which decodes the visual streams (133 and 135) and the audio streams (134 and 136) and performs seamless reproduction on the boundary detected by the seamless detection unit (107).