Abstract: A piezoelectric element includes, in sequence, a substrate, a lower electrode layer, a growth control layer, a piezoelectric layer including a perovskite-type oxide containing lead as a main component of an A site, and an upper electrode layer. The growth control layer includes a metal oxide represented by MdN1?dOe, where M is one or more metal elements capable of substituting for the A site of the perovskite-type oxide. When the electronegativity of M is X, 1.41X?1.05?d?A1·exp(?X/t1)+y0, where A1=1.68×1012, t1=0.0306, and y0=0.59958. The perovskite-type oxide is represented by (Pba1?a2)(Zrb1Tib2?b3)Oc, where 0.5<a1/(b1+b2+b3)<1.07.

Abstract: An imprint apparatus executes imprint processing of curing imprint material in a state in which the imprint material supplied onto a substrate and a mold are in contact with each other. The imprint apparatus includes a modulator configured to modulate incident light, a first optical system configured to guide first light from a first light source to the modulator, and second light from a second light source that has a wavelength different from that of the first light to the modulator, and a second optical system configured to guide modulated light modulated by the modulator to the substrate.

Abstract: An imprint apparatus executes imprint processing of curing imprint material in a state in which the imprint material supplied onto a substrate and a mold are in contact with each other. The imprint apparatus includes a modulator configured to modulate incident light, a first optical system configured to guide first light from a first light source to the modulator, and second light from a second light source that has a wavelength different from that of the first light to the modulator, and a second optical system configured to guide modulated light modulated by the modulator to the substrate.

Abstract: The present technology relates to a solid-state imaging device, a driving method, and an electronic device capable of suppressing leakage of charge from PD to FD. In a solid-state imaging device according to an aspect of the present technology, in a case where the charge is read out from a selected photoelectric conversion unit as a charge readout target out of the plurality of photoelectric conversion units sharing the shared holding unit to the shared holding unit, a drive control unit applies a first pulse to the readout unit that corresponds to the selected photoelectric conversion unit, and applies a second pulse having a polarity opposite to a polarity of the first pulse and having a pulse period overlapping with at least a portion of the pulse period of the first pulse, to a site coming into a capacitive coupling state with the shared holding unit. The present technology is applicable to a back-illumination CMOS image sensor, for example.

Abstract: A power down detection circuit and a semiconductor storage apparatus, which can adjust a power down detection level while suppressing temperature dependence, are provided. The power down detection circuit includes a BGR circuit, a trimming circuit, a resistance division circuit, and a comparator. The BGR circuit generates a reference voltage based on a supply voltage. The trimming circuit adjusts the reference voltage based on a trimming signal to generate a reference voltage for power down detection. The resistance division circuit generates an internal voltage lower than the supply voltage. The comparator detects that the internal voltage is lower than the reference voltage for power down detection and outputs a reset signal.

Abstract: A semiconductor device and an operation method capable of operating with high reliability are provided. A voltage monitoring circuit (100) of the disclosure includes: a power-on detection part (110) configurated to detect whether a supply voltage (EXVDD) of an external power supply terminal has reached a power-on voltage level; a timer (120) configurated to measure a predetermined time when the power-on voltage level is detected; a through current generation part (130) configurated to generate a through current between the external power supply terminal and GND during a period when the timer (120) measures the predetermined time; and a power-off detection part (140) configurated to detect whether a drop of the supply voltage (EXVDD) has reached a power-off voltage level when the through current is generated.

Abstract: A flash memory having high reliability and a method for controlling the flash memory is provided for seeking stability of memory cell threshold voltage distribution. A NAND string of the flash memory has: a source-line-side select transistor; a source-line-side dummy cell; a plurality of memory cells; a bit-line-side dummy cell; and a bit-line-side select transistor. A method for controlling the flash memory includes the following step: after erasing a selected block, programming the dummy cell of the selected block into a programmed state by applying a programming voltage to a dummy word line which is connected to the dummy cell.

Abstract: A power down detection circuit and a semiconductor storage apparatus, which can adjust a power down detection level while suppressing temperature dependence, are provided. The power down detection circuit includes a BGR circuit, a trimming circuit, a resistance division circuit, and a comparator. The BGR circuit generates a reference voltage based on a supply voltage. The trimming circuit adjusts the reference voltage based on a trimming signal to generate a reference voltage for power down detection. The resistance division circuit generates an internal voltage lower than the supply voltage. The comparator detects that the internal voltage is lower than the reference voltage for power down detection and outputs a reset signal.

Abstract: A flash memory having high reliability and a method for controlling the flash memory is provided for seeking stability of memory cell threshold voltage distribution. A NAND string of the flash memory has: a source-line-side select transistor; a source-line-side dummy cell; a plurality of memory cells; a bit-line-side dummy cell; and a bit-line-side select transistor. A method for controlling the flash memory includes the following step: after erasing a selected block, programming the dummy cell of the selected block into a programmed state by applying a programming voltage to a dummy word line which is connected to the dummy cell.

Abstract: A semiconductor storage device achieving stabilization of an operating voltage of a selected memory chip. A flash memory device of the disclosure includes a master chip and at least one slave chip. A voltage output portion of a charge pump circuit of the master chip is connected to an internal pad of the master chip, and a voltage output portion of a charge pump circuit of the slave chip is connected to an internal pad of the slave chip, the internal pad of the master chip and the internal pad of the slave chip are connected by a wire. When the mater chip is operated, the charge pump circuit of the master chip is turned off, the charge pump circuit of the slave chip is turned on, and a voltage generated by the charge pump circuit of the slave chip is supplied to the master chip.

Abstract: A semiconductor memory device facilitating an area efficiency of a page buffer/sense circuit and suppressing erroneous operation due to capacitive coupling between wires is provided. The flash memory 100 of the disclosure includes a memory cell array 110 and a page buffer/sense circuit 170. The memory cell array 110 includes a plurality of memory cells. The page buffer/sense circuit 170 holds data read from a page selected by the memory cell array 110 or holds data to be programmed to a page selected by the memory cell array 110. The page buffer/sense circuit 170 is arranged in n columns×m segments within one pitch in a row direction defined by p number of bit lines extending from the memory cell array 110. n is an integer of 2 or more then 2, and m is an integer of 2 or more then 2.

Abstract: A semiconductor storage device achieving stabilization of an operating voltage of a selected memory chip. A flash memory device of the disclosure includes a master chip and at least one slave chip. A voltage output portion of a charge pump circuit of the master chip is connected to an internal pad of the master chip, and a voltage output portion of a charge pump circuit of the slave chip is connected to an internal pad of the slave chip, the internal pad of the master chip and the internal pad of the slave chip are connected by a wire. When the mater chip is operated, the charge pump circuit of the master chip is turned off, the charge pump circuit of the slave chip is turned on, and a voltage generated by the charge pump circuit of the slave chip is supplied to the master chip.

Abstract: A semiconductor memory device facilitating an area efficiency of a page buffer/sense circuit and suppressing erroneous operation due to capacitive coupling between wires is provided. The flash memory 100 of the disclosure includes a memory cell array 110 and a page buffer/sense circuit 170. The memory cell array 110 includes a plurality of memory cells. The page buffer/sense circuit 170 holds data read from a page selected by the memory cell array 110 or holds data to be programmed to a page selected by the memory cell array 110. The page buffer/sense circuit 170 is arranged in n columns×m segments within one pitch in a row direction defined by p number of bit lines extending from the memory cell array 110. n is an integer of 2 or more then 2, and m is an integer of 2 or more then 2.

Abstract: Provided is a flash memory device capable of restricting power consumption in an erase operation. The invention includes a plurality of wells, a power supply device, and a coupling device. The power supply device applies erase voltages to the wells for performing an erase operation. The coupling device performs selective coupling between the wells. When performing the erase operation on the wells, the power supply device applies the erase voltage to one of the wells, and applies the erase voltage to the other one of the wells after the coupling device electrically couples the one of the wells to the other one of the wells.

Abstract: Provided is a flash memory device capable of restricting power consumption in an erase operation. The invention includes a plurality of wells, a power supply device, and a coupling device. The power supply device applies erase voltages to the wells for performing an erase operation. The coupling device performs selective coupling between the wells. When performing the erase operation on the wells, the power supply device applies the erase voltage to one of the wells, and applies the erase voltage to the other one of the wells after the coupling device electrically couples the one of the wells to the other one of the wells.

Abstract: Provided is a catalyst structure which prevents an increase in pressure loss by a simple construction while the gas flow is efficiently stirred by a structure making contact between adjacent catalyst elements. The catalyst structure is provided with a first flat-plate part and a second flat-plate part which support, on surfaces thereof, a constituent having catalytic activity to an exhaust gas and face each other, and a stirring part which is provided in such a manner as to come into contact first with the first flat-plate part and the second flat-plate part in an extending manner from the first flat-plate part to the second flat-plate part at a prescribed angle with respect to the direction in which the exhaust gas flows.

Abstract: A solid-state imaging device according to an embodiment includes a first semiconductor layer of a first conductivity type, a photodiode region in which a second semiconductor layer of a second conductivity type is formed in a surface of the first semiconductor layer, a first interlayer insulating film which is formed on the first semiconductor layer and on the photodiode region, a first fixed charge film which is formed on the first interlayer insulating film and has a charge of the second conductivity type, a second interlayer insulating film which is formed on or above the first fixed charge film, and a second fixed charge film which is formed on the second interlayer insulating film and has a charge of the second conductivity type.

Abstract: A semiconductor memory device, which restrains a breakdown of a low-voltage transistor constructing a bit line selecting circuit, is provided. An NAND string unit and transistors (BLSe, BLso, BIASe, BIASo) that construct bit line selecting circuit are formed in a P-well. The transistors are set in a floating state during erasing operation. The voltages of the transistors are increased when an erasing voltage is applied to the P-well. When the erasing voltage is discharged from the P-well, the gates of the transistors are connected to a reference potential via a discharging circuit (410) such that the gate voltage follows the voltage of the P-well to be discharged.

Abstract: A semiconductor memory device, which restrains a breakdown of a low-voltage transistor constructing a bit line selecting circuit, is provided. An NAND string unit and transistors (BLSe, BLso, BIASe, BIASo) that construct bit line selecting circuit are formed in a P-well. The transistors are set in a floating state during erasing operation. The voltages of the transistors are increased when an erasing voltage is applied to the P-well. When the erasing voltage is discharged from the P-well, the gates of the transistors are connected to a reference potential via a discharging circuit (410) such that the gate voltage follows the voltage of the P-well to be discharged.

Abstract: The invention provides a current detection circuit and a semiconductor memory apparatus using the current detection circuit thereof. The current detection circuit is capable of rapidly sensing the current flowing through a tiny bit line structure. A page buffer/sensing circuit of the invention includes: a transistor TP3 pre-charging a node SNS during a pre-charge period and providing a target constant current to the node SNS during a discharge period; a transistor TN3 pre-charging the bit line according to the voltage pre-charged to the node SNS; and a transistor TP2 connected to the node SNS. The transistor TP2 detects whether or not a current larger than the constant current supplied by the transistor TP3 is discharged from the bit line and outputs a detection result to a node SENSE.