Abstract: A data relay apparatus stores identification information for identifying itself. A blocking unit blocks a port to avoid an occurrence of a loop path if the data relay apparatus is a master node, and blocks a port connected to a link of the data relay apparatus if a failure occurs to the link. When the link is restored from the failure, a comparing unit compares identification information of other apparatus connected to the link, with the identification information stored. Based on a result of the comparison, a determining unit determines whether the data relay apparatus should be set as a master node.

Abstract: A bridge apparatus is provided, which apparatus includes a tag attaching mechanism for attaching a plurality of VLAN tags to a frame, a queue configured to store the frame according to the VLAN tags attached thereto, and a read control unit configured to control a read rate for reading the frame from the queue. The VLAN tags are stacked, and a first VLAN tag of the stacked VLAN tags is used for user identification, and a second VLAN tag of the stacked VLAN tags is used for base location route identification. Also, band control is conducted based on the VLAN tags.

Abstract: A packet switch device having a plurality of input buffers; a packet switch; a plurality of schedulers, having a pipeline scheduling process module wherein a plurality of time units corresponding to the number of output lines is spent in scheduled sending process of the fixed length packets from the input buffer, and wherein the scheduled sending process is executed in a number of processes, in parallel, the number of processes corresponding to the number of the input lines, having a sending status management module wherein sending status of the fixed length packets which constitute one frame is managed for each of the input lines, and provided corresponding to any of the output lines; and at least one result notification module for notifying the input buffer of result information from the scheduled sending process performed by each of the plurality of schedulers.

Abstract: A packet insertion interval control system includes a counting unit (32), having a first bit field for managing an insertion interval of a management packet required to be cyclically inserted and a second bit field for specifying a logic path for forwarding the management packet, for executing such a counting operation as to periodically cycle the first bit field and the second bit field, and a control unit (31) for executing control for specifying, when a count value indicated by the first bit field of the counting unit is a predetermined value, the logic path for forwarding the management packet on the basis of a count value indicated by the second bit field of the counting unit, and for inserting the management packet into the specified logic path. With this architecture, it is feasible to restrain an increase in quantity of the hardware and flexibly correspond to changes in the number of connections (number of channels) and the cell insertion interval (packet insertion interval) per communication system.

Abstract: The invention relates to a bandwidth control apparatus in ATM equipment, for inserting management cells such as OAM cells, the control apparatus being configured to secure a bandwidth for the insertion of a management cell such as an OAM cell when the need arises, while guaranteeing the service quality of user cells, thereby making effective use of network resources for a best effort service such as ABR or UBR.

Abstract: In an ATM switching system, an ABR service is implemented with a specific ABR control capability. A subscriber line processing device includes calculating a turnaround delay time of a cell, based on a period during which the cell doubles back at a terminal. A switch or a demultiplexer capable of detecting congestion. A rate calculator calculates a transmission rate corresponding to an output channel, and writes the calculated rate to the cell. A rate changer changes the transmission rate according to congestion. The rate changer counts the number of communicating connections. Then the number of communicating connections which should exist in a certain predetermined period is estimated based on the counted number of communicating connections. A coefficient is determined based on the estimated number of communicating connections and an actual number of communicating connections, and a next estimated value is estimated using the coefficient.

Abstract: A packet switch which can cyclically use &agr; scheduling process results to determine one of M output lines as a destination of a packet stored in each of N input buffer sections by &agr; scheduler sections independently performing scheduling processes is disclosed.

Abstract: A packet multiplexing control method and equipment using the method are realized by a simple control method with reduced hardware, enabling to provide low cost, efficient and fair bandwidth control corresponding to traffic characteristic of users. The packet multiplexing control method includes the steps of extracting a header part in each packet data received from a plurality of terminals; learning an address in the extracted header part; and controlling either admission processing or discard processing of the received packet according to the result of learning the address.

Abstract: An input line interface device that is used to accommodate packets from a high-speed line efficiently and to reduce a processing load on a back stage caused by routing control. A packet allotting section divides a variable-length packet, allots divided packets to parallel lines, and outputs the packets. A flow group classifying section classifies the packets into flow groups on each of the parallel lines. A sequence number giving section gives the packets sequence numbers corresponding to or independent of the flow groups. A buffering section stores the packets to which the sequence numbers have been given in a buffer or reads out them from the buffer to exercise sequence control over the packets in the flow groups. A flow separating switch separates the packets according to the flow groups and outputs the packets.

Abstract: A scheduling method includes the steps of processing scheduling processes of all input lines according to a processing sequence in which a highest priority output line of a highest priority input line is processed with a first priority, in an environment in which a plurality of processing sequences have different scheduling targets among a plurality of input lines, and updating the highest priority input line and the highest priority output line of each input line for every scheduling cycle.

Abstract: The packet switch performs a scheduling process by selecting a unicast packet or a multicast packet to be output from each of N input buffers such that input lines and output lines cannot conflict each other for a unicast packet, and such that the input lines cannot conflict each other for the multicast packet.

Abstract: A packet switch which can cyclically use &agr; scheduling process results to determine one of M output lines as a destination of a packet stored in each of N input buffer sections by &agr; scheduler sections independently performing scheduling processes is disclosed.

Abstract: Packets input from input HWs #0 to #3 to a packet switch device are buried in time slots A through D. The packet switch device alternately switches the input packets in units of time slots, and inputs the packets to two 4×4 switches. The 4×4 switches make normal switching, and distribute the packets to respective output ports. Then, the packets output from the two 4×4 switches after being switched are alternately multiplexed, and output to output HWs #0 through #3. By making switching in units of packets as described above, a process overhead is prevented from being increased, and also expansion can be easily made. Besides, hardware scale can be made small.

Abstract: A buffer unit fragments variable-length packets into fixed-length packets for processing in units of fixed-length packets. The buffer unit includes a fixed-length packet storing section for storing the fixed-length packets for each of output paths, a multicasting processor for storing multicasting packets having a plurality of destinations and transferring the multicasting packets to the fixed-length packet storing section depending on the plurality of destinations, and a controller for monitoring a storage state of the fixed-length packet storing section and carrying out a control so that the multicasting packets are transferred within a variable-length packet formed by a plurality of fixed-length packets.

Abstract: To achieve QoS control, drop control and multicast control of a variable-length packet at high speed in small scale hardware, a packet divider divides a variable-length packet into fixed-length packets, and an input buffer section stores the divided fixed-length packets into queues by output lines and by QoS classes. A large number of QoS classes are mapped into only two kinds of classes including a guaranteed bandwidth class for which an assigned bandwidth is guaranteed and a best effort class for which a surplus bandwidth is allocated, thereby to achieve scheduling at the input side by an inter-line scheduler. An output buffer section assembles a variable-length packet from fixed-length packets that have been obtained by switching at a switch section in an output buffer section. A QoS control is performed based on a packet length.

Abstract: A packet insertion interval control system includes a counting unit (32), having a first bit field for managing an insertion interval of a management packet required to be cyclically inserted and a second bit field for specifying a logic path for forwarding the management packet, for executing such a counting operation as to periodically cycle the first bit field and the second bit field, and a control unit (31) for executing control for specifying, when a count value indicated by the first bit field of the counting unit is a predetermined value, the logic path for forwarding the management packet on the basis of a count value indicated by the second bit field of the counting unit, and for inserting the management packet into the specified logic path. With this architecture, it is feasible to restrain an increase in quantity of the hardware and flexibly correspond to changes in the number of connections (number of channels) and the cell insertion interval (packet insertion interval) per communication system.

Abstract: A packet switch device having a plurality of input buffers; a packet switch; a plurality of schedulers, having a pipeline scheduling process module wherein a plurality of time units corresponding to the number of output lines is spent in scheduled sending process of the fixed length packets from the input buffer, and wherein the scheduled sending process is executed in a number of processes, in parallel, the number of processes corresponding to the number of the input lines, having a sending status management module wherein sending status of the fixed length packets which constitute one frame is managed for each of the input lines, and provided corresponding to any of the output lines; and at least one result notification module for notifying the input buffer of result information from the scheduled sending process performed by each of the plurality of schedulers.

Abstract: Specific ABR control capability for implementing an ABR service in an ATM switching system. A subscriber line processing device has a capability for calculating a turnaround delay time of a cell, based on a period during which the cell loops back at a terminal and returns. A switch or demultiplexer has a capability for detecting congestion. A rate calculator calculates a transmission rate corresponding to an output channel, and writes the calculated rate to the cell. A rate changer suitably changes the transmission rate according to the degree of occurrence of congestion. Additionally, the rate changer counts the number of communicating connections. At this time, the number of communicating connections which should exist in a certain predetermined period is estimated based on the counted number of communicating connections, which is counted in a period shorter than the predetermined period according to a predetermined method.