Patents by Inventor Kenichi Maeda

Kenichi Maeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160267027
    Abstract: According to one embodiment, a memory device includes a nonvolatile memory, a volatile memory, a controller, and a board. The nonvolatile memory stores data. The volatile memory holds a part of the data stored in the nonvolatile memory. The memory controller controls the volatile memory and the nonvolatile memory. The nonvolatile memory, the volatile memory, and the memory controller are provided on the board. The memory controller transmits an interrupt signal to a request source, when the volatile memory does not have any data corresponding to an address which the request source requests to access.
    Type: Application
    Filed: July 24, 2015
    Publication date: September 15, 2016
    Inventors: Toshio Fujisawa, Nobuhiro Kondo, Shoji Sawamura, Kenichi Maeda, Atsushi Kunimatsu
  • Patent number: 9424252
    Abstract: An information providing device: saves a posted document and respective electronic files of a translation thereof in one or more other languages, in association with one another; issues a code image including a two-dimensional code created by encoding a two-dimensional code character string for identifying the electronic file associated with the same identification information; receives, from a user terminal device that accesses the electronic file by decoding the two-dimensional code from the document on which the code image is printed, character code data indicating the language set in the user terminal device, and transmits the electronic file of the translation translated into the language indicated by the character code data to the user terminal device together with information that indicates the posting place of the document, thereby providing the translation and the information that indicates the posting place of the document.
    Type: Grant
    Filed: April 2, 2012
    Date of Patent: August 23, 2016
    Assignee: PIJIN CO. LTD.
    Inventors: Kenji Takaoka, Takao Yano, Masayasu Iwashima, Kenichi Maeda, Zhichen Geng
  • Patent number: 9396141
    Abstract: According to embodiments a memory system is connectable to a host which includes a host controller and a host memory including a first memory area and a second memory area. The memory system includes an interface unit, a non-volatile memory, and a controller unit. The interface unit receives a read command and a write command. The controller unit writes write-data to the non-volatile memory according to the write command. The controller unit determines whether read-data requested by the read command is in the first memory area. If the read-data is in the first memory area, the controller unit causes the host controller to copy the read-data from the first memory area to the second memory area. If the read-data is not in the first memory area, the controller unit reads the read-data from the non-volatile memory and causes the host controller to store the read-data in the second memory area.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: July 19, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenichi Maeda, Nobuhiro Kondo, Kenichiro Yoshii, Keigo Hara, Toshio Fujisawa
  • Patent number: 9385378
    Abstract: Provided herein is a lead-acid battery for which the risk of breakage of a current collecting lug part of a plate while in use is eliminated by simple means. At least a positive plate group of the lead-acid battery includes: one or more plates each including a current collector having a current collecting portion formed by expanding or punching a lead alloy sheet manufactured by cold rolling, and one or more current collecting lug parts unitarily formed with the current collecting portion; and a strap formed by a cast-on strap casting method and coupled to the one or more current collecting lug parts. The current collecting lug part is formed with an elongated protrusion extending in a direction away from the current collecting portion. The elongated protrusion continuously extends in a direction toward the current collecting portion of the plate from inside the strap.
    Type: Grant
    Filed: March 6, 2015
    Date of Patent: July 5, 2016
    Assignee: Hitachi Chemical Company, Ltd.
    Inventors: Hiroki Tsuji, Masatoshi Miyatsuka, Kazuya Sasaki, Naoki Tsuji, Kenichi Maeda, Yoshifumi Yamada
  • Patent number: 9336065
    Abstract: According to one embodiment, a semiconductor device includes a processor, and a memory device. The memory device has a nonvolatile semiconductor storage device and is configured to serve as a main memory for the processor. When the processor executes a plurality of programs, the processor manages pieces of information required to execute the programs as worksets for the respective programs, and creates tables, which hold relationships between pieces of information required for the respective worksets and addresses of the pieces of information in the memory device, for the respective worksets. The processor accesses to the memory device with reference to the corresponding tables for the respective worksets.
    Type: Grant
    Filed: October 8, 2014
    Date of Patent: May 10, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroto Nakai, Kenichi Maeda, Tatsunori Kanai
  • Publication number: 20160098226
    Abstract: A device includes a host including a main memory, and semiconductor memory including a nonvolatile semiconductor memory, memory unit, and controller. The nonvolatile semiconductor memory stores first address information. The memory unit stores second address information as part of the first address information. The controller accesses the nonvolatile semiconductor memory based on the second address information. Third address information is stored in the main memory, and is part or all of the first address information. The controller uses the third address information when accessing the nonvolatile semiconductor memory if address information to be referred is not stored in the second address information.
    Type: Application
    Filed: December 10, 2015
    Publication date: April 7, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Atsushi KUNIMATSU, Kenichi MAEDA
  • Publication number: 20160071158
    Abstract: According to one embodiment, a storage unit, a management unit that acquires attributes of communication apparatuses from a plurality of the communication apparatuses and stores identifiers of the communication apparatuses and the attributes in the storage unit in association with each other as communication apparatus information, and a selection unit that selects a distributor apparatus that is the communication apparatus distributing a content to the other communication apparatuses as a radio signal based on the communication apparatus information are included.
    Type: Application
    Filed: December 23, 2014
    Publication date: March 10, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Arata MIYAMOTO, Kenichi Maeda, Masahiro Ishiyama, Shinya Murai, Hiroto Nakai
  • Patent number: 9282522
    Abstract: According to the embodiments, when a communication apparatus is a publisher, a transmission message including a first identifier is transmitted using first transmission power, when the communication apparatus is a subscriber, data of a reception message including the first identifier is stored in a nonvolatile memory, when at least a part of the reception message cannot be received, a repair message for requesting retransmission of the reception message is transmitted from a wireless interface unit using second transmission power, and when there is no response, a repair message is transmitted using third transmission power that is larger than the second transmission power.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: March 8, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenichi Maeda, Arata Miyamoto, Masahiro Ishiyama, Hiroto Nakai
  • Patent number: 9280466
    Abstract: A device according to an example of the invention comprises a section which accepts a write destination logical address and write target data from a processor, the write destination logical address indicating a write position to write the write target data into a composite memory which includes a first memory and a nonvolatile second memory, a section which determines a write destination physical address corresponding to the write destination logical address so that the number of times of access to the second memory is smaller than the number of times of access to the first memory, a section which stores, in a storage section, address conversion data associating the write destination logical address with the write destination physical address, and a section which writes the write target data into a position in the composite memory indicated by the write destination physical address.
    Type: Grant
    Filed: September 9, 2009
    Date of Patent: March 8, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Atsushi Kunimatsu, Hiroto Nakai, Hiroyuki Sakamoto, Kenichi Maeda, Masaki Miyagawa, Hiroshi Nozue, Kazuhiro Kawagome
  • Publication number: 20160062660
    Abstract: A memory management device of an example of the invention controls writing into and reading from a main memory including a nonvolatile semiconductor memory and a volatile semiconductor memory in response to a writing request and a reading request from a processor. The memory management device includes a coloring information storage unit that stores coloring information generated based on a data characteristic of write target data to be written into at least one of the nonvolatile semiconductor memory and the volatile semiconductor memory, and a writing management unit that references the coloring information to determines a region into which the write target data is written from the nonvolatile semiconductor memory and the volatile semiconductor memory.
    Type: Application
    Filed: November 11, 2015
    Publication date: March 3, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Atsushi KUNIMATSU, Masaki MIYAGAWA, Hiroshi NOZUE, Kazuhiro KAWAGOME, Hiroto NAKAI, Hiroyuki SAKAMOTO, Tsutomu OWA, Tsutomu UNESAKI, Reina NISHINO, Kenichi MAEDA, Mari TAKADA
  • Publication number: 20160054943
    Abstract: According to one embodiment, an information processing apparatus includes a memory system and a host. The memory system includes a nonvolatile first memory and a first control unit. The host includes a volatile second memory and a second control unit. The second memory includes a first area which is used by the host and a second area which is used by the memory system. The second control unit transmits an access request to the first control unit. The access request contains an address. The first control unit determines whether an access destination is the first memory or the second area based on the address and accesses the determined access destination.
    Type: Application
    Filed: March 3, 2015
    Publication date: February 25, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kenichiro YOSHII, Kenichi MAEDA, Nobuhiro KONDO
  • Patent number: 9268706
    Abstract: A device includes a host including a main memory, and semiconductor memory including a nonvolatile semiconductor memory, memory unit, and controller. The nonvolatile semiconductor memory stores first address information. The memory unit stores second address information as part of the first address information. The controller accesses the nonvolatile semiconductor memory based on the second address information. Third address information is stored in the main memory, and is part or all of the first address information. The controller uses the third address information when accessing the nonvolatile semiconductor memory if address information to be referred is not stored in the second address information.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: February 23, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Atsushi Kunimatsu, Kenichi Maeda
  • Publication number: 20160041871
    Abstract: According to one embodiment, an information processing apparatus includes a host and a memory system. The memory system includes a nonvolatile memory. The host includes a volatile memory, a first host control unit, and a second host control unit. The volatile memory includes a first area to be used by the host and a second area as a cache memory to temporarily store data of the nonvolatile memory. The first host control unit computes a first code, and stores the first data and the first code in the second area. The first code is redundant information of the first data. The second host control unit reads second data and a second code from the second area, performs error detection on the second data based on the second code, and transfers the second data. The second code is redundant information of the second data.
    Type: Application
    Filed: February 27, 2015
    Publication date: February 11, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kenichi MAEDA, Nobuhiro KONDO, Kenichiro YOSHII, Satoshi KABURAKI
  • Patent number: 9249712
    Abstract: An air-fuel ratio control system for an internal combustion engine, which, at the resumption of air-fuel ratio feedback control, is capable of setting the initial value of an integral term of the feedback control to a value properly learned in preceding feedback control, thereby enabling improvement of control accuracy. To feedback-control the output value of an O2 sensor to a target value, a target air-fuel ratio is calculated. During the feedback control, when it is determined that a predetermined condition in which it is estimated that exhaust gas air-fuel ratio upstream of the catalyst is excellently reflected on an exhaust gas air-fuel ratio at a location midway or downstream of the catalyst is satisfied, an adaptive law input calculated immediately before interruption of the feedback control is updated and stored as the initial value of an integral term for the following execution of the feedback control.
    Type: Grant
    Filed: June 10, 2011
    Date of Patent: February 2, 2016
    Assignee: HONDA MOTOR CO., LTD.
    Inventors: Michinori Tani, Kenichi Maeda, Atsuhiro Miyauchi, Seiji Watanabe, Soichiro Goto
  • Publication number: 20160008408
    Abstract: [Problem] To provide a method for producing human corneal epithelial sheet, wherein the human corneal epithelial-derived cells obtained by culturing human corneal epithelial cells are cultured on an amnion substrate. [Solution] A method for culturing human corneal epithelial cells using mesenchymal stem cells as the feeder cells; and a method for culturing human corneal epithelial cells using a medium containing a ROCK inhibitor, a phosphodiesterase inhibitor, a MAP kinase inhibitor and a TGF-? receptor inhibitor in various combinations.
    Type: Application
    Filed: March 9, 2014
    Publication date: January 14, 2016
    Applicants: JCR PHARMACEUTICALS CO., LTD., KYOTO PREFECTURAL PUBLIC UNIVERSITY CORPORATION
    Inventors: Kiwamu IMAGAWA, Kenichi MAEDA, Yuki HOSODA, Shuichi YOKOYAMA, Naoki OKUMURA, Noriko KOIZUMI, Shigeru KINOSHITA
  • Patent number: 9223724
    Abstract: A device of one embodiment includes a host device including a first memory unit and host controller, and memory device. The host controller controls input/output accesses to the first memory unit. The memory device includes a nonvolatile semiconductor memory, second memory unit, protection circuit, and device controller. The second memory unit temporarily stores data to be transferred between the first memory unit and the nonvolatile semiconductor memory. The protection circuit protects data to be transferred from the second memory unit to the first memory unit by converting the data into an incomprehensible format. The device controller switches according to a control program whether or not to protect the data by the protection circuit.
    Type: Grant
    Filed: January 23, 2014
    Date of Patent: December 29, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Nobuhiro Kondo, Konosuke Watanabe, Kenichi Maeda
  • Publication number: 20150365202
    Abstract: According to one embodiment, a communication apparatus includes an operation mode storage unit configured to store whether the communication apparatus is in a mode to operate as a radio base station or a mode to operate as a terminal, and a non-volatile memory. In a case of the radio base station, a message to be transmitted is output to the outside. In a case of the terminal, data included in a received message is stored in the non-volatile memory. In a case of operating as the radio base station, the operation mode is changed from the terminal to the radio base station when communication quality with an external first radio base station is less than a predetermined value and a message from a radio base station other than the first radio base station is not received after all the data transmitted by the first radio base station have been received.
    Type: Application
    Filed: September 11, 2014
    Publication date: December 17, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hiroki Kudo, Masahiro Ishiyama, Kenichi Maeda, Arata Miyamoto, Hiroto Nakai
  • Publication number: 20150296349
    Abstract: A mode of a publisher or a subscriber is stored. Also, a first identifier indicating affiliation to a first group is stored. In a case of the publisher, a transmission message including ToC information, which is a list of the first identifiers and data to be transmitted, is transmitted to an outside. In a case of the subscriber, when a received message includes the first identifier, data included in the message is stored into a non-volatile memory, and when it is determined that all data in the ToC information stored in the received message are already received and that the number of publishers is less than a threshold, the stored mode is changed to the publisher.
    Type: Application
    Filed: September 11, 2014
    Publication date: October 15, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masahiro ISHIYAMA, Arata MIYAMOTO, Kenichi MAEDA, Hiroki KUDO, Hiroto NAKAI
  • Publication number: 20150177985
    Abstract: According to one embodiment, an information processing device includes: a host device, a semiconductor memory device with a nonvolatile semiconductor memory, and a communication path connecting the host device and the semiconductor memory device together.
    Type: Application
    Filed: March 3, 2015
    Publication date: June 25, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Nobuhiro Kondo, Kenichi Maeda
  • Publication number: 20150180048
    Abstract: Provided herein is a lead-acid battery for which the risk of breakage of a current collecting lug part of a plate while in use is eliminated by simple means. At least a positive plate group of the lead-acid battery includes: one or more plates each including a current collector having a current collecting portion formed by expanding or punching a lead alloy sheet manufactured by cold rolling, and one or more current collecting lug parts unitarily formed with the current collecting portion; and a strap formed by a cast-on strap casting method and coupled to the one or more current collecting lug parts. The current collecting lug part is formed with an elongated protrusion extending in a direction away from the current collecting portion. The elongated protrusion continuously extends in a direction toward the current collecting portion of the plate from inside the strap.
    Type: Application
    Filed: March 6, 2015
    Publication date: June 25, 2015
    Inventors: Hiroki TSUJI, Masatoshi MIYATSUKA, Kazuya SASAKI, Naoki TSUJI, Kenichi MAEDA, Yoshifumi YAMADA