Patents by Inventor Kenichi Otsuka
Kenichi Otsuka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 5834367Abstract: In a method of manufacturing a semiconductor device having a multilayer wiring structure, it has at least two underlying layers having different etching conditions. Firstly, the native oxide film formed on one of the underlying layers, or a barrier metal layer, is etched out under etching conditions suitable for the barrier metal layer. Then, the surface of the barrier metal layer is capped with a plugging material having etching conditions similar to or substantially the same as those of the other one of the underlying layers, or a lower wiring layer. Subsequently, the native oxide film and the etching by-product formed on the lower wiring layer are etched out under etching conditions suitable for the lower wiring layer. Thereafter, contact holes for the two underlying layers are buried with a conductive substance to establish electric connection with their respective upper conductive layers.Type: GrantFiled: April 12, 1996Date of Patent: November 10, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Mari Otsuka, Kenichi Otsuka
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Patent number: 5759912Abstract: An Al alloy interconnection layer is deposited on a silicon oxide layer, and a first carbon layer is formed on the Al alloy interconnection layer. Then, the first carbon layer and the Al alloy interconnection layer are patterned, thereby forming a first interconnection layer consisting of the Al alloy interconnection layer and the first carbon layer. Sequentially, a second carbon layer is formed on the first interconnection layer and the silicon oxide layer. The second carbon layer is entirely etched by the RIE method, thereby leaving the second carbon layer only on side surfaces of the first interconnection layer. A high temperature layer made of SiO.sub.2 is deposited on the second carbon layer, the first interconnection layer and the silicon oxide layer. Thereafter, the high temperature layer is etched back until the first carbon layer is exposed, thus being flattened. An interlayer insulating layer is deposited on the high temperature layer and the first interconnection layer.Type: GrantFiled: May 28, 1996Date of Patent: June 2, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Kazuya Mori, Kenichi Otsuka
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Patent number: 5607878Abstract: An inter-level insulation film is formed on a first-level interconnection layer and part of the inter-level insulation film which lies on the first-level interconnection layer is etched to form a contact hole. After a natural oxidation film formed on the surface of part of the first-level interconnection layer which is exposed in the contact hole is removed, the resultant structure is exposed to a gas atmosphere containing halogen to purify the surface of the inter-level insulation film. After this, a contact plug is deposited and formed on the first-level interconnection layer which is exposed in the contact hole by the selective CVD method to fill in the contact hole. A second-level interconnection layer is formed on the inter-level insulation film and the first-level and second-level interconnection layers are electrically connected to each other via the contact plug.Type: GrantFiled: September 12, 1995Date of Patent: March 4, 1997Assignee: Kabushiki Kaisha ToshibaInventors: Mari Otsuka, Tomonori Kitakura, Kenichi Otsuka, Kazuya Mori
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Patent number: 5498571Abstract: An Al alloy interconnection layer is deposited on a silicon oxide layer, and a first carbon layer is formed on the Al alloy interconnection layer. Then, the first carbon layer and the Al alloy interconnection layer are patterned, thereby forming a first interconnection layer consisting of the Al alloy interconnection layer and the first carbon layer. Sequentially, a second carbon layer is formed on the first interconnection layer and the silicon oxide layer. The second carbon layer is entirely etched by the RIE method, thereby leaving the second carbon layer only on side surfaces of the first interconnection layer. A high temperature layer made of SiO.sub.2 is deposited on the second carbon layer, the first interconnection layer and the silicon oxide layer. Thereafter, the high temperature layer is etched back until the first carbon layer is exposed, thus being flattened. An interlayer insulating layer is deposited on the high temperature layer and the first interconnection layer.Type: GrantFiled: June 1, 1995Date of Patent: March 12, 1996Assignee: Kabushiki Kaisha ToshibaInventors: Kazuya Mori, Kenichi Otsuka
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Patent number: 5496393Abstract: A gas purification apparatus has two gas purification units which are alternately operated. A gas purification capacity measuring means includes a means including valves for separating a target gas purification unit from a line, an evacuating means for evacuating the separated gas purification unit at a high vacuum, a means including a supply tank for supplying a predetermined very small amount of an impurity gas to an inlet of the high-vacuum separated gas purification unit, an auxiliary tank (e.g., a pressure reduction tank, a metering tank, and a pressure reduction valve), and a vacuum gauge for measuring a change in pressure at the outlet upon supply of the impurity gas to the inlet. In the gas purification apparatus having gas purification units each incorporating a getter material, the gas purification capacity of each gas purification unit can be more accurately and easily measured.Type: GrantFiled: May 15, 1995Date of Patent: March 5, 1996Assignee: Kabushiki Kaisha ToshibaInventors: Kenichi Otsuka, Kazuya Mori
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Patent number: 5225245Abstract: An apparatus for forming, by a chemical vapor deposition process, a thin film of crystals such as diamond on a surface of a heated substrate placed in a reaction vessel. The apparatus has a substrate supporting structure, a heater for heating the substrate by heat conduction or by electric current supplied directly to the substrate, and a cooling device for cooling the substrate. The heater is controlled in accordance with the measured temperature of the substrate so as to accurately maintain the substrate temperature at a constant level.Type: GrantFiled: August 17, 1990Date of Patent: July 6, 1993Assignee: Kawasaki Steel CorporationInventors: Tomohiro Ohta, Eiichi Kondoh, Tohru Mitomo, Kenichi Otsuka, Hiroshi Sekihashi
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Patent number: 5209182Abstract: An apparatus for forming, by a chemical vapor deposition process, a thin film of crystals such as diamond on a surface of a heated substrate placed in a reaction vessel. The apparatus has a substrate supporting structure, a heater for heating the substrate by heat conduction or by electric current supplied directly to the substrate, and a cooling device for cooling the substrate. The heater is controlled in accordance with the measured temperature of the substrate so as to accurately maintain the substrate temperature at a constant level.Type: GrantFiled: April 29, 1992Date of Patent: May 11, 1993Assignee: Kawasaki Steel CorporationInventors: Tomohiro Ohta, Eiichi Kondoh, Tohru Mitomo, Kenichi Otsuka, Hiroshi Sekihashi
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Patent number: 4810285Abstract: In a process for preparing a spherical copper fine powder having an average grain size ranging from 0.1 .mu.m to a few .mu.m, by use of chemical vapor deposition of cuprous chloride vapor with a reducing gas, the vapor deposition zone is maintained at a temperature ranging 900.degree. C. to less than 1,150.degree. C. and the generated particles are quenched subsequently. The generated powder is utilized as a conductive powder which is the main component of a conductive paste.Type: GrantFiled: March 18, 1988Date of Patent: March 7, 1989Assignee: Kawasaki Steel CorporationInventors: Kenichi Otsuka, Minoru Nitta
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Patent number: 4502132Abstract: A supporting insulator (9) to support the driving mechanism (6) of a disconnect switch part (100) and a supporting insulator (9) of a breaker (10) are unified. The heights of the fixed contact (4) and the driving mechanism (6) of the disconnect switch part (100) as well as the height of the upper end of the common supporting insulator (9) supporting the breaker (10) are substantially the same. Setting area is thus decreased, while ensuring a high spatial insulation distance.Type: GrantFiled: October 4, 1983Date of Patent: February 26, 1985Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Akira Nishikawa, Toru Saito, Kenichi Otsuka
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Patent number: 4482855Abstract: A current control apparatus includes an instructor for providing a DC amplitude instruction and an AC phase instruction, and a cycloconverter for supplying an induction motor with AC load currents. These load currents are detected by sensors. The sensed signals from the sensors are applied to a detector. The detector generates a DC phase error signal and a DC amplitude signal according to the load currents and the phase instruction. The amplitude instruction, amplitude signal and phase error signal are applied to a comparator circuit. The comparator circuit generates a first voltage instruction and a second voltage instruction. These first and second voltage instructions are applied to a control circuit. The control circuit supplies the cycloconverter with voltage instructions. The comparator circuit, control circuit, cycloconverter, sensors and detector constitute a closed DC feedback control loop which utilizes a vector control method.Type: GrantFiled: May 17, 1983Date of Patent: November 13, 1984Assignee: Tokyo Shibaura Denki Kabushiki KaishaInventors: Kenichi Otsuka, Takeo Shimamura
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Patent number: 4371440Abstract: Newly isolated yeasts assimilating a high amount of protein are added to a waste water rich in protein thereby making such yeasts assimilate protein, so that the B.O.D. of the waste water is efficiently decreased.Type: GrantFiled: September 23, 1981Date of Patent: February 1, 1983Assignees: National Tax Administration Agency, Toh Zinc Company LimitedInventors: Kiyoshi Yoshizawa, Kenichi Otsuka, Kikuo Nojiro, Takeo Koizumi, Katsuyoshi Mitsutomi, Seiji Nakamura
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Patent number: 4349867Abstract: A control apparatus for a cycloconverter includes m sets of bridge converters connected between the input terminals of an m-phase load (m.gtoreq.3) and is applied for a cycloconverter of which the common connection point of the bridge converters is disconnected from a neutral point of the load. The output voltage of each bridge converter is controlled by a reference voltage signal during a 1/m period of one cycle of the load voltage. The center of the 1/m period is located at a positive or negative maximum amplitude point of the load voltage. The output voltage is also controlled during the remaining period of (1-1/m) by a phase control input signal corresponding to a difference between a reference current signal and the load current. The reference voltage signal and the phase control input signal are selected by switching signals from a logic circuit for detecting phase voltages of the load to alternately be applied to the phase control circuits.Type: GrantFiled: March 6, 1981Date of Patent: September 14, 1982Assignee: Tokyo Shibaura Denki Kabushiki KaishaInventors: Kenichi Otsuka, Hiroshi Uchino, Kihei Nakajima
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Patent number: 4325112Abstract: A voltage source inverter has a main circuit with a switching device to which is connected a DC power source through a load, and a control circuit for controlling the on-off operation of the switching device. The control circuit includes a function generator for outputting a first signal representative of the voltage-time-integration value in correspondence with the phase of the load voltage, a time counter for outputting a second signal representative of total time of the integrated time of the period during which the DC voltage is applied to the load, and a comparator for comparing the first signal with the second signal. The output of the comparator controls the on-off operation of the switching device through a logic circuit and supplies a pulse-width-modulated AC voltage to the load.Type: GrantFiled: January 5, 1981Date of Patent: April 13, 1982Assignee: Tokyo Shibaura Denki Kabushiki KaishaInventor: Kenichi Otsuka
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Patent number: 4295079Abstract: A lamp circuit is provided having a constant current type AC power source and a plurality of isolation transformers connected in series with the AC power source. The secondary circuit of each isolation transformer is connected to an electric lamp. The voltage-time area, which is measured from the rise of the voltage output signal of the power source to the rise of the current output signal of the power source is detected and is compared with a reference predetermined value. Thereby when the detected value exceeds the reference value an alarm signal is generated and the number of the disconnected lamps can be determined and displayed.Type: GrantFiled: March 25, 1980Date of Patent: October 13, 1981Assignee: Tokyo Shibaura Denki Kabushiki KaishaInventors: Kenichi Otsuka, Yorio Hosokawa