Abstract: A semiconductor nonvolatile memory device which enables shortening of the time of the bit verification operation and thus high speed reading operations, including a first memory cell array connected to a first bit line, a second memory cell array connected to a second bit line, a first transistor operatively connecting the first bit line and a first node, a second transistor operatively connecting the second bit line and a second node, a precharging circuit for precharging the first and second bit lines, and an equalizing circuit for equalizing the sense amplifier, wherein, at the time of a verification read operation, the gate electrode of the transistor connected to the bit line on the reference side is given as input a control signal set to a level not more than a voltage comprised of the precharge voltage of that bit line plus the threshold voltage of that transistor.