Patents by Inventor Kenichi Shimbo

Kenichi Shimbo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9933475
    Abstract: Provided is a semiconductor inspection circuit which is capable of inspecting connection states of power supply, ground, and signal bumps in a semiconductor package or a printed circuit board equipped with a semiconductor LSI mounted in a product operation state. As a means to solve the problem, a circuit capable of switching a path is provided at an input portion of a driver/receiver, a mechanism capable of transferring an output of a path switching circuit near a receiver circuit to a voltage waveform circuit with an internal variable terminal is provided, and a breakage state of a bump can be observed in the product operation state by observing a DC level at a terminal having a certain DC resistance when a signal bump connection state is observed and receiving a step wave and observing a response waveform thereof when an IO power supply bump connection state is observed.
    Type: Grant
    Filed: April 24, 2015
    Date of Patent: April 3, 2018
    Assignee: HITACHI, LTD.
    Inventors: Yutaka Uematsu, Hideki Osaka, Tadanobu Toba, Kenichi Shimbo
  • Publication number: 20170350933
    Abstract: Provided is a semiconductor inspection circuit which is capable of inspecting connection states of power supply, ground, and signal bumps in a semiconductor package or a printed circuit board equipped with a semiconductor LSI mounted in a product operation state. As a means to solve the problem, a circuit capable of switching a path is provided at an input portion of a driver/receiver, a mechanism capable of transferring an output of a path switching circuit near a receiver circuit to a voltage waveform circuit with an internal variable terminal is provided, and a breakage state of a bump can be observed in the product operation state by observing a DC level at a terminal having a certain DC resistance when a signal bump connection state is observed and receiving a step wave and observing a response waveform thereof when an IO power supply bump connection state is observed.
    Type: Application
    Filed: April 24, 2015
    Publication date: December 7, 2017
    Inventors: Yutaka UEMATSU, Hideki OSAKA, Tadanobu TOBA, Kenichi SHIMBO
  • Patent number: 9749542
    Abstract: In an output destination decoder, a desired area receiver receives a desired area, and a cutting-out unit cuts out a desired area from an image input from an output source, and displays the image in the desired area which is cut out.
    Type: Grant
    Filed: May 28, 2014
    Date of Patent: August 29, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kenichi Shimbo, Hironori Terauchi, Ichio Motegi
  • Patent number: 9645871
    Abstract: For a soft error of an electronic device, a technique capable of ensuring high reliability because of a low soft error rate (SER) is provided. By using building data including information of a structural object of a building and facility data including information of a plurality of facilities including an electronic device arranged in the building, a SER calculating device calculates a model including an attenuation index value representing a degree of attenuation of radiation entering the building attenuated by the structural object of the building until the radiation reaches a position of the facility arranged in the building, calculates a SER at each position of the facility arranged in the building by using the model including the attenuation index value, and outputs information including the SER at each position of the facility.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: May 9, 2017
    Assignee: Hitachi, Ltd.
    Inventors: Kenichi Shimbo, Tadanobu Toba, Takumi Uezono
  • Patent number: 9507895
    Abstract: A simulation apparatus includes a discrete events simulation section to perform a discrete type simulation of components of a configured model as defined based on attribute information that is information on parts of the components of the defined configured model and connection information showing a connectional relationship among the components of the defined configured model; and a soft error rate computation processing section to compute a soft error rate of the defined configured model based on the simulation result of the discrete events simulation section and data on soft error rates in the attribute information.
    Type: Grant
    Filed: May 13, 2011
    Date of Patent: November 29, 2016
    Assignee: HITACHI, LTD.
    Inventors: Tadanobu Toba, Kenichi Shimbo, Hidefumi Ibe, Hideki Osaka
  • Publication number: 20160335145
    Abstract: The present invention aims to provide a programmable device with a configuration memory that can hold the state of the occurrence abnormal situation that is difficult to assume such as a failure occurring in the programmable device due to the terrestrial radiation of the configuration memory, even during power off, in order to improve the reproducibility in device testing based on the held error information. The programmable device with the configuration memory includes: an error detection section for detecting an error in the configuration memory, and outputting the detected error as well as an address in which the error occurred, as error information; and an error information holding section provided with a non-volatile memory to store the output error information.
    Type: Application
    Filed: January 24, 2014
    Publication date: November 17, 2016
    Inventors: Tadanobu TOBA, Kenichi SHIMBO, Yusuke KANNO, Nobuyasu KANEKAWA, Kotara SHIMAMURA, Hiromichi YAMADA
  • Publication number: 20160085605
    Abstract: For a soft error of an electronic device, a technique capable of ensuring high reliability because of a low soft error rate (SER) is provided. By using building data including information of a structural object of a building and facility data including information of a plurality of facilities including an electronic device arranged in the building, a SER calculating device calculates a model including an attenuation index value representing a degree of attenuation of radiation entering the building attenuated by the structural object of the building until the radiation reaches a position of the facility arranged in the building, calculates a SER at each position of the facility arranged in the building by using the model including the attenuation index value, and outputs information including the SER at each position of the facility.
    Type: Application
    Filed: May 24, 2013
    Publication date: March 24, 2016
    Inventors: Kenichi SHIMBO, Tadanobu TOBA, Takumi UEZONO
  • Publication number: 20160057355
    Abstract: In an output destination decoder, a desired area receiver 43 receives a desired area, and a cutting-out unit 44 cuts out a desired area from an image input from an output source, and displays the image in the desired area which is cut out.
    Type: Application
    Filed: May 28, 2014
    Publication date: February 25, 2016
    Applicant: Mitsubishi Electric Corporation
    Inventors: Kenichi SHIMBO, Hironori TERAUCHI, Ichio MOTEGI
  • Patent number: 8904233
    Abstract: A failure caused by a soft-error including MNU, of an electronic apparatus is prevented, while suppressing increase of a mounting area, power consumption, and processing time. The electronic apparatus stores data indicating the state of a flip-flop included in a sequential logic circuit within an arithmetic unit, each time when execution is performed on a check point provided for every predetermined number of instructions. When a symptom of a soft-error is detected, the apparatus sets the state of the flip-flop included in the sequential logic circuit within the arithmetic unit, based on the data stored after execution of the instruction at the immediately preceding check point, and restarts execution from the next instruction, being subsequent to the instruction associated with the immediately preceding check point.
    Type: Grant
    Filed: February 9, 2011
    Date of Patent: December 2, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Hidefumi Ibe, Tadanobu Toba, Kenichi Shimbo, Hitoshi Taniguchi
  • Publication number: 20140164839
    Abstract: In the event of a software error, operations of a programmable device must be suspended while a configuration memory is being rewritten; however, with a system such as a communication device that will be significantly affected if the device is shut down, the system needs to be restored without suspending the operations.
    Type: Application
    Filed: June 25, 2012
    Publication date: June 12, 2014
    Inventors: Tadanobu Toba, Kenichi Shimbo
  • Publication number: 20130132056
    Abstract: A simulation apparatus includes a discrete events simulation section to perform a discrete type simulation of components of a configured model as defined based on attribute information that is information on parts of the components of the defined configured model and connection information showing a connectional relationship among the components of the defined configured model; and a soft error rate computation processing section to compute a soft error rate of the defined configured model based on the simulation result of the discrete events simulation section and data on soft error rates in the attribute information.
    Type: Application
    Filed: May 13, 2011
    Publication date: May 23, 2013
    Inventors: Tadanobu Toba, Kenichi Shimbo, Hidefumi Ibe, Hideki Osaka
  • Publication number: 20120304005
    Abstract: A failure caused by a soft-error including MNU, of an electronic apparatus is prevented, while suppressing increase of a mounting area, power consumption, and processing time. The electronic apparatus stores data indicating the state of a flip-flop included in a sequential logic circuit within an arithmetic unit, each time when execution is performed on a check point provided for every predetermined number of instructions. When a symptom of a soft-error is detected, the apparatus sets the state of the flip-flop included in the sequential logic circuit within the arithmetic unit, based on the data stored after execution of the instruction at the immediately preceding check point, and restarts execution from the next instruction, being subsequent to the instruction associated with the immediately preceding check point.
    Type: Application
    Filed: February 9, 2011
    Publication date: November 29, 2012
    Inventors: Hidefumi Ibe, Tadanobu Toba, Kenichi Shimbo, Hitoshi Taniguchi
  • Patent number: 7783437
    Abstract: An arc monitor system locates an arc based on optimal frames from a frame obtained before an arc discharge to a frame obtained immediately after the arc discharge. The arc monitor system, used to locate an occurred place of an arc discharge that occurred in an electric facility, includes multiple monitor cameras arranged at multiple places in the electric facility, an image processing device that processes images received from the respective monitor cameras, a control logic section that controls the image processing device, and an operation device that includes a display section and an operation section and is connected to the control logic section. The image processing device and the control logic section extract a change in the images received from the monitor cameras in response to a control signal generated from the electric facility on an occurrence of the arc discharge, and then locate an occurred place of the arc discharge.
    Type: Grant
    Filed: September 22, 2004
    Date of Patent: August 24, 2010
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Chubu Electric Power Co., Inc.
    Inventors: Yoshihisa Oguchi, Kenichi Shimbo, Atsushi Suzuki, Toshiya Kumai, Hisaya Saitou
  • Publication number: 20070108990
    Abstract: An arc monitor system locates an arc based on optimal frames from a frame obtained before an arc discharge to a frame obtained immediately after the arc discharge. The arc monitor system, used to locate an occurred place of an arc discharge that occurred in an electric facility, includes multiple monitor cameras arranged at multiple places in the electric facility, an image processing device that processes images received from the respective monitor cameras, a control logic section that controls the image processing device, and an operation device that includes a display section and an operation section and is connected to the control logic section. The image processing device and the control logic section extract a change in the images received from the monitor cameras in response to a control signal generated from the electric facility on an occurrence of the arc discharge, and then locate an occurred place of the arc discharge.
    Type: Application
    Filed: September 22, 2004
    Publication date: May 17, 2007
    Applicant: CHUBU ELECTRIC POWER CO., INC.
    Inventors: Yoshihisa Oguchi, Kenichi Shimbo, Atsushi Suzuki, Toshiya Kumai, Hisaya Saitou